EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# FE310-G000
#
DEF FE310-G000 U 0 20 Y Y 1 F N
F0 "U" -1000 1150 50 H V L CNN
F1 "FE310-G000" 500 1150 50 H V L CNN
F2 "Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm_ThermalVias" 100 -1150 50 H I C CNN
F3 "" -1100 1250 50 H I C CNN
ALIAS FE310-G002
$FPLIST
 QFN*1EP*6x6mm*P0.4mm*
$ENDFPLIST
DRAW
S -1000 1100 1000 -1100 0 1 10 f
X QSPI_DQ_3 1 -1100 -100 100 R 50 50 1 1 B
X XTAL_XO 10 -1100 900 100 R 50 50 1 1 O
X IVDD 11 100 1200 100 D 50 50 1 1 W
X OTP_AIVDD 12 300 1200 100 D 50 50 1 1 W
X JTAG_TCK 13 -1100 700 100 R 50 50 1 1 I
X JTAG_TDO 14 -1100 600 100 R 50 50 1 1 O
X JTAG_TMS 15 -1100 500 100 R 50 50 1 1 I
X JTAG_TDI 16 -1100 400 100 R 50 50 1 1 I
X AON_PMU_OUT_1 17 -1100 -600 100 R 50 50 1 1 O
X ~AON_PMU_DWAKEUP 18 -1100 -700 100 R 50 50 1 1 I
X AON_IVDD 19 -200 1200 100 D 50 50 1 1 W
X QSPI_DQ_2 2 -1100 0 100 R 50 50 1 1 B
X AON_PSD_LFALTCLK 20 -1100 -900 100 R 50 50 1 1 I
X AON_PSD_LFCLKSEL 21 -1100 -1000 100 R 50 50 1 1 I
X AON_PMU_OUT_0 22 -1100 -500 100 R 50 50 1 1 O
X AON_VDD 23 -300 1200 100 D 50 50 1 1 W
X ~AON_ERST 24 -1100 -800 100 R 50 50 1 1 I
X GPIO_0 25 1100 900 100 L 50 50 1 1 B
X GPIO_1 26 1100 800 100 L 50 50 1 1 B
X GPIO_2 27 1100 700 100 L 50 50 1 1 B
X GPIO_3 28 1100 600 100 L 50 50 1 1 B
X GPIO_4 29 1100 500 100 L 50 50 1 1 B
X QSPI_DQ_1 3 -1100 100 100 R 50 50 1 1 B
X VDD 30 0 1200 100 D 50 50 1 1 P N
X GPIO_5 31 1100 400 100 L 50 50 1 1 B
X IVDD 32 100 1200 100 D 50 50 1 1 P N
X GPIO_9 33 1100 300 100 L 50 50 1 1 B
X GPIO_10 34 1100 200 100 L 50 50 1 1 B
X GPIO_11 35 1100 100 100 L 50 50 1 1 B
X GPIO_12 36 1100 0 100 L 50 50 1 1 B
X GPIO_13 37 1100 -100 100 L 50 50 1 1 B
X GPIO_16 38 1100 -200 100 L 50 50 1 1 B
X GPIO_17 39 1100 -300 100 L 50 50 1 1 B
X QSPI_DQ_0 4 -1100 200 100 R 50 50 1 1 B
X GPIO_18 40 1100 -400 100 L 50 50 1 1 B
X GPIO_19 41 1100 -500 100 L 50 50 1 1 B
X GPIO_20 42 1100 -600 100 L 50 50 1 1 B
X GPIO_21 43 1100 -700 100 L 50 50 1 1 B
X GPIO_22 44 1100 -800 100 L 50 50 1 1 B
X GPIO_23 45 1100 -900 100 L 50 50 1 1 B
X VDD 46 0 1200 100 D 50 50 1 1 P N
X IVDD 47 100 1200 100 D 50 50 1 1 P N
X QSPI_SCK 48 -1100 -300 100 R 50 50 1 1 O
X GND 49 0 -1200 100 U 50 50 1 1 W
X ~QSPI_CS 5 -1100 -200 100 R 50 50 1 1 O
X VDD 6 0 1200 100 D 50 50 1 1 W
X PLL_AVDD 7 400 1200 100 D 50 50 1 1 W
X PLL_AVSS 8 200 -1200 100 U 50 50 1 1 W
X XTAL_XI 9 -1100 1000 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# FU540-C000
#
DEF FU540-C000 U 0 20 Y Y 6 L N
F0 "U" 0 100 50 H V C CNN
F1 "FU540-C000" 0 -100 50 H V C CNN
F2 "Package_BGA:BGA-484_23.0x23.0mm_Layout22x22_P1.0mm" 0 0 50 H I C CNN
F3 "" 0 5000 50 H I C CNN
$FPLIST
 BGA*23.0x23.0mm*P1.0mm*
$ENDFPLIST
DRAW
S -900 -1800 900 1800 1 1 10 f
S -1100 -4800 1100 4800 2 1 10 f
S -1000 -900 1000 900 3 1 10 f
S -800 -1500 800 1400 4 1 10 f
S -900 -1300 900 1300 5 1 10 f
S -800 -700 800 700 6 1 10 f
X CL_0_B2C_D_2 AA18 -1100 1400 200 R 50 50 1 1 I
X CL_0_B2C_D_8 AA19 -1100 800 200 R 50 50 1 1 I
X CL_0_B2C_D_23 AA20 -1100 -700 200 R 50 50 1 1 I
X CL_0_B2C_D_29 AA21 -1100 -1300 200 R 50 50 1 1 I
X CL_0_B2C_CLK AA22 -1100 1700 200 R 50 50 1 1 I
X CL_0_B2C_D_1 AB18 -1100 1500 200 R 50 50 1 1 I
X CL_0_B2C_D_13 AB19 -1100 300 200 R 50 50 1 1 I
X CL_0_B2C_D_22 AB20 -1100 -600 200 R 50 50 1 1 I
X CL_0_B2C_D_26 AB21 -1100 -1000 200 R 50 50 1 1 I
X CL_0_C2B_D_28 K19 1100 -1200 200 L 50 50 1 1 O
X CL_0_C2B_D_24 K20 1100 -800 200 L 50 50 1 1 O
X CL_0_C2B_D_26 K22 1100 -1000 200 L 50 50 1 1 O
X CL_0_C2B_D_31 L17 1100 -1500 200 L 50 50 1 1 O
X CL_0_C2B_D_30 L18 1100 -1400 200 L 50 50 1 1 O
X CL_0_C2B_D_27 L19 1100 -1100 200 L 50 50 1 1 O
X CL_0_C2B_D_20 L20 1100 -400 200 L 50 50 1 1 O
X CL_0_C2B_D_18 L21 1100 -200 200 L 50 50 1 1 O
X CL_0_C2B_D_29 L22 1100 -1300 200 L 50 50 1 1 O
X CL_0_C2B_D_15 M17 1100 100 200 L 50 50 1 1 O
X CL_0_C2B_D_19 M18 1100 -300 200 L 50 50 1 1 O
X CL_0_C2B_D_23 M19 1100 -700 200 L 50 50 1 1 O
X CL_0_C2B_D_12 M20 1100 400 200 L 50 50 1 1 O
X CL_0_C2B_D_25 M21 1100 -900 200 L 50 50 1 1 O
X CL_0_C2B_D_22 M22 1100 -600 200 L 50 50 1 1 O
X CL_0_C2B_SEND N17 1100 -1700 200 L 50 50 1 1 O
X CL_0_C2B_D_2 N18 1100 1400 200 L 50 50 1 1 O
X CL_0_C2B_D_6 N19 1100 1000 200 L 50 50 1 1 O
X CL_0_C2B_D_21 N20 1100 -500 200 L 50 50 1 1 O
X CL_0_C2B_D_16 N21 1100 0 200 L 50 50 1 1 O
X CL_0_C2B_D_14 N22 1100 200 200 L 50 50 1 1 O
X CL_0_B2C_RST P17 -1100 -1600 200 R 50 50 1 1 I
X CL_0_B2C_D_21 P18 -1100 -500 200 R 50 50 1 1 I
X CL_0_C2B_CLK P19 1100 1700 200 L 50 50 1 1 O
X CL_0_C2B_D_4 P20 1100 1200 200 L 50 50 1 1 O
X CL_0_B2C_D_24 R17 -1100 -800 200 R 50 50 1 1 I
X CL_0_B2C_D_17 R18 -1100 -100 200 R 50 50 1 1 I
X CL_0_C2B_D_1 R19 1100 1500 200 L 50 50 1 1 O
X CL_0_C2B_D_3 R20 1100 1300 200 L 50 50 1 1 O
X CL_0_C2B_D_8 R21 1100 800 200 L 50 50 1 1 O
X CL_0_C2B_D_17 R22 1100 -100 200 L 50 50 1 1 O
X CL_0_B2C_D_19 T18 -1100 -300 200 R 50 50 1 1 I
X CL_0_C2B_D_0 T19 1100 1600 200 L 50 50 1 1 O
X CL_0_C2B_RST T20 1100 -1600 200 L 50 50 1 1 O
X CL_0_C2B_D_13 T21 1100 300 200 L 50 50 1 1 O
X CL_0_C2B_D_10 T22 1100 600 200 L 50 50 1 1 O
X CL_0_B2C_D_20 U17 -1100 -400 200 R 50 50 1 1 I
X CL_0_B2C_D_14 U18 -1100 200 200 R 50 50 1 1 I
X CL_0_B2C_D_18 U19 -1100 -200 200 R 50 50 1 1 I
X CL_0_C2B_D_5 U20 1100 1100 200 L 50 50 1 1 O
X CL_0_C2B_D_11 U21 1100 500 200 L 50 50 1 1 O
X CL_0_C2B_D_7 U22 1100 900 200 L 50 50 1 1 O
X CL_0_B2C_D_12 V16 -1100 400 200 R 50 50 1 1 I
X CL_0_B2C_D_16 V17 -1100 0 200 R 50 50 1 1 I
X CL_0_B2C_D_9 V18 -1100 700 200 R 50 50 1 1 I
X CL_0_B2C_D_15 V19 -1100 100 200 R 50 50 1 1 I
X CL_0_B2C_D_25 V20 -1100 -900 200 R 50 50 1 1 I
X CL_0_B2C_D_4 W16 -1100 1200 200 R 50 50 1 1 I
X CL_0_B2C_D_3 W17 -1100 1300 200 R 50 50 1 1 I
X CL_0_B2C_D_5 W18 -1100 1100 200 R 50 50 1 1 I
X CL_0_B2C_D_11 W19 -1100 500 200 R 50 50 1 1 I
X CL_0_B2C_D_28 W20 -1100 -1200 200 R 50 50 1 1 I
X CL_0_B2C_SEND W21 -1100 -1700 200 R 50 50 1 1 I
X CL_0_C2B_D_9 W22 1100 700 200 L 50 50 1 1 O
X CL_0_B2C_D_0 Y16 -1100 1600 200 R 50 50 1 1 I
X CL_0_B2C_D_7 Y17 -1100 900 200 R 50 50 1 1 I
X CL_0_B2C_D_6 Y18 -1100 1000 200 R 50 50 1 1 I
X CL_0_B2C_D_10 Y19 -1100 600 200 R 50 50 1 1 I
X CL_0_B2C_D_27 Y20 -1100 -1100 200 R 50 50 1 1 I
X CL_0_B2C_D_31 Y21 -1100 -1500 200 R 50 50 1 1 I
X CL_0_B2C_D_30 Y22 -1100 -1400 200 R 50 50 1 1 I
X DDR_MEM_D[18] A4 1300 1800 200 L 50 50 2 1 B
X DDR_MEM_D[19] A5 1300 1900 200 L 50 50 2 1 B
X DDR_MEM_DQS_P[2] A6 1300 1500 200 L 50 50 2 1 B
X DDR_MEM_DQS_M[2] A7 1300 1400 200 L 50 50 2 1 B
X DDR_MEM_D[41] AA1 1300 -1900 200 L 50 50 2 1 B
X DDR_MEM_D[61] AA10 1300 -3900 200 L 50 50 2 1 B
X DDR_MEM_D[63] AA11 1300 -3700 200 L 50 50 2 1 B
X DDR_MEM_D[58] AA12 1300 -4200 200 L 50 50 2 1 B
X DDR_MEM_D[56] AA13 1300 -4400 200 L 50 50 2 1 B
X DDR_MEM_D[45] AA3 1300 -1500 200 L 50 50 2 1 B
X DDR_MEM_D[47] AA4 1300 -1300 200 L 50 50 2 1 B
X DDR_MEM_ODT[0] AA5 -1300 -100 200 R 50 50 2 1 O
X DDR_MEM_CKE[1] AA6 -1300 -400 200 R 50 50 2 1 O
X DDR_MEM_DQS_M[6] AA7 1300 -3400 200 L 50 50 2 1 B
X DDR_MEM_DQS_P[7] AA8 1300 -4500 200 L 50 50 2 1 B
X DDR_MEM_D[62] AA9 1300 -3800 200 L 50 50 2 1 B
X DDR_MEM_D[60] AB11 1300 -4000 200 L 50 50 2 1 B
X DDR_MEM_DM[7] AB12 1300 -4700 200 L 50 50 2 1 B
X DDR_MEM_D[44] AB2 1300 -1600 200 L 50 50 2 1 B
X DDR_MEM_D[46] AB3 1300 -1400 200 L 50 50 2 1 B
X DDR_MEM_ODT[1] AB5 -1300 -200 200 R 50 50 2 1 O
X DDR_MEM_CKE[0] AB6 -1300 -300 200 R 50 50 2 1 O
X DDR_MEM_D[57] AB8 1300 -4300 200 L 50 50 2 1 B
X DDR_MEM_D[59] AB9 1300 -4100 200 L 50 50 2 1 B
X DDR_MEM_D[1] B1 1300 4100 200 L 50 50 2 1 B
X DDR_MEM_D[17] B2 1300 1700 200 L 50 50 2 1 B
X DDR_MEM_D[22] B3 1300 2200 200 L 50 50 2 1 B
X DDR_MEM_D[16] B4 1300 1600 200 L 50 50 2 1 B
X DDR_MEM_D[20] B5 1300 2000 200 L 50 50 2 1 B
X DDR_MEM_D[23] B6 1300 2300 200 L 50 50 2 1 B
X DDR_MEM_D[4] C1 1300 4400 200 L 50 50 2 1 B
X DDR_MEM_D[29] C2 1300 900 200 L 50 50 2 1 B
X DDR_MEM_D[27] C3 1300 700 200 L 50 50 2 1 B
X DDR_MEM_D[24] C4 1300 400 200 L 50 50 2 1 B
X DDR_MEM_D[21] C5 1300 2100 200 L 50 50 2 1 B
X DDR_MEM_DM[2] C6 1300 1300 200 L 50 50 2 1 B
X DDR_MEM_D[31] C7 1300 1100 200 L 50 50 2 1 B
X DDR_MEM_D[0] D2 1300 4000 200 L 50 50 2 1 B
X DDR_MEM_D[30] D3 1300 1000 200 L 50 50 2 1 B
X DDR_MEM_D[25] D4 1300 500 200 L 50 50 2 1 B
X DDR_MEM_DM[3] D5 1300 100 200 L 50 50 2 1 B
X DDR_MEM_D[26] D6 1300 600 200 L 50 50 2 1 B
X DDR_MEM_DQS_M[3] D7 1300 200 200 L 50 50 2 1 B
X DDR_RSVD1 D8 -1300 -2700 200 R 50 50 2 1 P
X DDR_MEM_D[6] E1 1300 4600 200 L 50 50 2 1 B
X DDR_MEM_D[3] E2 1300 4300 200 L 50 50 2 1 B
X DDR_MEM_DM[0] E5 1300 3700 200 L 50 50 2 1 B
X DDR_MEM_D[28] E6 1300 800 200 L 50 50 2 1 B
X DDR_MEM_DQS_P[3] E7 1300 300 200 L 50 50 2 1 B
X DDR_RSVD0 E8 -1300 -2600 200 R 50 50 2 1 P
X DDR_MEM_D[9] F1 1300 2900 200 L 50 50 2 1 B
X DDR_MEM_DQS_P[0] F2 1300 3900 200 L 50 50 2 1 B
X DDR_MEM_DQS_M[0] F3 1300 3800 200 L 50 50 2 1 B
X DDR_MEM_D[2] F4 1300 4200 200 L 50 50 2 1 B
X DDR_MEM_D[10] F5 1300 3000 200 L 50 50 2 1 B
X DDR_CAL_0 F6 -1300 -4700 200 R 50 50 2 1 P
X DDR_RSVD2 F8 -1300 -2800 200 R 50 50 2 1 P
X DDR_RSVD3 F9 -1300 -2900 200 R 50 50 2 1 P
X DDR_MEM_D[11] G1 1300 3100 200 L 50 50 2 1 B
X DDR_MEM_D[7] G3 1300 4700 200 L 50 50 2 1 B
X DDR_MEM_D[5] G4 1300 4500 200 L 50 50 2 1 B
X DDR_MEM_DM[1] G5 1300 2500 200 L 50 50 2 1 B
X DDR_MEM_D[12] H1 1300 3200 200 L 50 50 2 1 B
X DDR_MEM_DQS_P[1] H2 1300 2700 200 L 50 50 2 1 B
X DDR_MEM_DQS_M[1] H3 1300 2600 200 L 50 50 2 1 B
X DDR_MEM_D[8] H4 1300 2800 200 L 50 50 2 1 B
X DDR_MEM_ECC_D[0] H5 -1300 -2000 200 R 50 50 2 1 B
X DDR_MEM_D[14] J2 1300 3400 200 L 50 50 2 1 B
X DDR_MEM_D[13] J3 1300 3300 200 L 50 50 2 1 B
X DDR_MEM_D[15] J4 1300 3500 200 L 50 50 2 1 B
X DDR_MEM_ECC_DM J5 -1300 -2300 200 R 50 50 2 1 B
X DDR_MEM_ECC_D[1] K1 -1300 -1900 200 R 50 50 2 1 B
X DDR_MEM_ECC_DQS_P K2 -1300 -2100 200 R 50 50 2 1 B
X DDR_MEM_ECC_DQS_M K3 -1300 -2200 200 R 50 50 2 1 B
X DDR_MEM_ECC_D[2] K4 -1300 -1800 200 R 50 50 2 1 B
X DDR_MEM_CLK K5 -1300 -1000 200 R 50 50 2 1 O
X DDR_MEM_ECC_D[4] L1 -1300 -1600 200 R 50 50 2 1 B
X DDR_MEM_ECC_D[3] L2 -1300 -1700 200 R 50 50 2 1 B
X DDR_MEM_ECC_D[7] L3 -1300 -1300 200 R 50 50 2 1 B
X DDR_MEM_ECC_D[5] L4 -1300 -1500 200 R 50 50 2 1 B
X DDR_MEM_CLK_N L5 -1300 -1100 200 R 50 50 2 1 O
X DDR_MEM_ECC_D[6] M1 -1300 -1400 200 R 50 50 2 1 B
X DDR_MEM_RAS_N M2 -1300 300 200 R 50 50 2 1 O
X DDR_MEM_CAS_N M3 -1300 400 200 R 50 50 2 1 O
X DDR_MEM_BANK[0] M4 -1300 500 200 R 50 50 2 1 O
X DDR_MEM_BANK[2] M5 -1300 700 200 R 50 50 2 1 O
X DDR_MEM_WE_N N1 -1300 200 200 R 50 50 2 1 O
X DDR_MEM_BANK[1] N2 -1300 600 200 R 50 50 2 1 O
X DDR_MEM_ADDR[0] N3 -1300 800 200 R 50 50 2 1 O
X DDR_MEM_ADDR[2] N4 -1300 1000 200 R 50 50 2 1 O
X DDR_MEM_ADDR[5] N5 -1300 1300 200 R 50 50 2 1 O
X DDR_MEM_ADDR[3] P3 -1300 1100 200 R 50 50 2 1 O
X DDR_MEM_ADDR[6] P4 -1300 1400 200 R 50 50 2 1 O
X DDR_MEM_ADDR[12] P5 -1300 2000 200 R 50 50 2 1 O
X DDR_MEM_ADDR[1] R1 -1300 900 200 R 50 50 2 1 O
X DDR_MEM_ADDR[7] R2 -1300 1500 200 R 50 50 2 1 O
X DDR_MEM_ADDR[8] R3 -1300 1600 200 R 50 50 2 1 O
X DDR_MEM_ADDR[11] R4 -1300 1900 200 R 50 50 2 1 O
X DDR_MEM_D[32] R5 1300 -800 200 L 50 50 2 1 B
X DDR_MEM_ADDR[4] T1 -1300 1200 200 R 50 50 2 1 O
X DDR_MEM_ADDR[13] T2 -1300 2100 200 R 50 50 2 1 O
X DDR_MEM_ADDR[9] T3 -1300 1700 200 R 50 50 2 1 O
X DDR_MEM_D[34] T4 1300 -600 200 L 50 50 2 1 B
X DDR_MEM_DM[4] T5 1300 -1100 200 L 50 50 2 1 B
X DDR_MEM_ADDR[10] U1 -1300 1800 200 R 50 50 2 1 O
X DDR_MEM_PARITY_IN U2 -1300 100 200 R 50 50 2 1 O
X DDR_MEM_ADDR[14] U3 -1300 2200 200 R 50 50 2 1 O
X DDR_MEM_DQS_M[4] U4 1300 -1000 200 L 50 50 2 1 B
X DDR_MEM_D[39] U5 1300 -100 200 L 50 50 2 1 B
X DDR_MEM_D[35] V2 1300 -500 200 L 50 50 2 1 B
X DDR_MEM_ADDR[15] V3 -1300 2300 200 R 50 50 2 1 O
X DDR_MEM_DQS_P[4] V4 1300 -900 200 L 50 50 2 1 B
X DDR_MEM_D[40] V5 1300 -2000 200 L 50 50 2 1 B
X DDR_MEM_D[33] W1 1300 -700 200 L 50 50 2 1 B
X DDR_MEM_DM[6] W10 1300 -3500 200 L 50 50 2 1 B
X DDR_MEM_D[49] W11 1300 -3100 200 L 50 50 2 1 B
X DDR_MEM_D[54] W12 1300 -2600 200 L 50 50 2 1 B
X DDR_MEM_D[38] W2 1300 -200 200 L 50 50 2 1 B
X DDR_MEM_D[37] W3 1300 -300 200 L 50 50 2 1 B
X DDR_MEM_DQS_M[5] W4 1300 -2200 200 L 50 50 2 1 B
X DDR_MEM_DM[5] W5 1300 -2300 200 L 50 50 2 1 B
X DDR_MEM_ERROR_N W6 -1300 0 200 R 50 50 2 1 I
X DDR_MEM_CS_N[1] W7 -1300 -600 200 R 50 50 2 1 O
X DDR_MEM_D[51] W8 1300 -2900 200 L 50 50 2 1 B
X DDR_MEM_D[55] W9 1300 -2500 200 L 50 50 2 1 B
X DDR_MEM_D[36] Y1 1300 -400 200 L 50 50 2 1 B
X DDR_MEM_D[52] Y10 1300 -2800 200 L 50 50 2 1 B
X DDR_MEM_D[50] Y11 1300 -3000 200 L 50 50 2 1 B
X DDR_MEM_D[48] Y12 1300 -3200 200 L 50 50 2 1 B
X DDR_MEM_D[43] Y2 1300 -1700 200 L 50 50 2 1 B
X DDR_MEM_D[42] Y3 1300 -1800 200 L 50 50 2 1 B
X DDR_MEM_DQS_P[5] Y4 1300 -2100 200 L 50 50 2 1 B
X DDR_MEM_RESET_N Y5 -1300 -700 200 R 50 50 2 1 O
X DDR_MEM_CS_N[0] Y6 -1300 -500 200 R 50 50 2 1 O
X DDR_MEM_DQS_P[6] Y7 1300 -3300 200 L 50 50 2 1 B
X DDR_MEM_DQS_M[7] Y8 1300 -4600 200 L 50 50 2 1 B
X DDR_MEM_D[53] Y9 1300 -2700 200 L 50 50 2 1 B
X GEMGXL_0_RXD_2 A10 -1200 400 200 R 50 50 3 1 I
X GEMGXL_0_RX_DV A11 -1200 -200 200 R 50 50 3 1 I
X GEMGXL_0_RXD_0 A12 -1200 600 200 R 50 50 3 1 I
X GEMGXL_0_COL A13 -1200 -500 200 R 50 50 3 1 I
X GEMGXL_0_RXD_5 A8 -1200 100 200 R 50 50 3 1 I
X GEMGXL_0_RXD_1 B10 -1200 500 200 R 50 50 3 1 I
X GEMGXL_0_RX_ER B11 -1200 -300 200 R 50 50 3 1 I
X GEMGXL_0_TXD_0 B12 1200 400 200 L 50 50 3 1 O
X GEMGXL_0_MDC B13 -1200 -700 200 R 50 50 3 1 O
X GEMGXL_0_TX_EN B7 1200 -400 200 L 50 50 3 1 O
X GEMGXL_0_TXD_6 B8 1200 -200 200 L 50 50 3 1 O
X GEMGXL_0_TXD_4 C10 1200 0 200 L 50 50 3 1 O
X GEMGXL_0_TXD_1 C11 1200 300 200 L 50 50 3 1 O
X GEMGXL_0_MDIO C12 -1200 -800 200 R 50 50 3 1 B
X GEMGXL_0_CRS C13 -1200 -400 200 R 50 50 3 1 I
X GEMGXL_0_TX_CLK C8 1200 500 200 L 50 50 3 1 I
X GEMGXL_0_RXD_6 C9 -1200 0 200 R 50 50 3 1 I
X GEMGXL_0_TXD_5 D10 1200 -100 200 L 50 50 3 1 O
X GEMGXL_0_TXD_2 D11 1200 200 200 L 50 50 3 1 O
X GEMGXL_0_TXD_7 D9 1200 -300 200 L 50 50 3 1 O
X GEMGXL_0_RXD_4 E10 -1200 200 200 R 50 50 3 1 I
X GEMGXL_0_RXD_3 E11 -1200 300 200 R 50 50 3 1 I
X GEMGXL_0_GTX_CLK E12 -1200 800 200 R 50 50 3 1 I
X GEMGXL_0_RXD_7 E9 -1200 -100 200 R 50 50 3 1 I
X GEMGXL_0_TX_ER F10 1200 -500 200 L 50 50 3 1 O
X GEMGXL_0_TXD_3 F11 1200 100 200 L 50 50 3 1 O
X GEMGXL_0_RX_CLK F12 -1200 700 200 R 50 50 3 1 I
X GPIO_0_P_9 A21 -1000 400 200 R 50 50 4 1 B
X UART_1_RXD AA14 1000 1000 200 L 50 50 4 1 I
X UART_1_TXD AA15 1000 1100 200 L 50 50 4 1 O
X QSPI_2_DQ_0 AA16 1000 700 200 L 50 50 4 1 B
X QSPI_2_CS_0 AB14 1000 300 200 L 50 50 4 1 O
X QSPI_2_DQ_1 AB15 1000 600 200 L 50 50 4 1 B
X QSPI_2_DQ_2 AB16 1000 500 200 L 50 50 4 1 B
X GPIO_0_P_11 B20 -1000 200 200 R 50 50 4 1 B
X GPIO_0_P_12 B21 -1000 100 200 R 50 50 4 1 B
X GPIO_0_P_14 B22 -1000 -100 200 R 50 50 4 1 B
X GPIO_0_P_7 C20 -1000 600 200 R 50 50 4 1 B
X GPIO_0_P_2 C21 -1000 1100 200 R 50 50 4 1 B
X GPIO_0_P_1 C22 -1000 1200 200 R 50 50 4 1 B
X GPIO_0_P_8 D19 -1000 500 200 R 50 50 4 1 B
X GPIO_0_P_5 D20 -1000 800 200 R 50 50 4 1 B
X GPIO_0_P_3 D21 -1000 1000 200 R 50 50 4 1 B
X PWM_1_P_0 D22 -1000 -1100 200 R 50 50 4 1 B
X GPIO_0_P_4 E18 -1000 900 200 R 50 50 4 1 B
X GPIO_0_P_13 E19 -1000 0 200 R 50 50 4 1 B
X GPIO_0_P_6 E20 -1000 700 200 R 50 50 4 1 B
X GPIO_0_P_0 F17 -1000 1300 200 R 50 50 4 1 B
X GPIO_0_P_10 F18 -1000 300 200 R 50 50 4 1 B
X PWM_1_P_3 F19 -1000 -1400 200 R 50 50 4 1 B
X PWM_0_P_2 F20 -1000 -900 200 R 50 50 4 1 B
X PWM_0_P_1 F21 -1000 -800 200 R 50 50 4 1 B
X QSPI_1_DQ_2 F22 1000 -900 200 L 50 50 4 1 B
X GPIO_0_P_15 G17 -1000 -200 200 R 50 50 4 1 B
X PWM_1_P_2 G18 -1000 -1300 200 R 50 50 4 1 B
X PWM_0_P_0 G19 -1000 -700 200 R 50 50 4 1 B
X PWM_0_P_3 G20 -1000 -1000 200 R 50 50 4 1 B
X QSPI_1_CS_1 G21 1000 -1200 200 L 50 50 4 1 O
X QSPI_1_DQ_0 G22 1000 -700 200 L 50 50 4 1 B
X PWM_1_P_1 H17 -1000 -1200 200 R 50 50 4 1 B
X QSPI_1_SCK H18 1000 -600 200 L 50 50 4 1 O
X QSPI_1_CS_2 H19 1000 -1300 200 L 50 50 4 1 O
X QSPI_0_DQ_3 H20 1000 -300 200 L 50 50 4 1 B
X QSPI_0_DQ_0 H21 1000 0 200 L 50 50 4 1 B
X QSPI_0_DQ_1 H22 1000 -100 200 L 50 50 4 1 B
X QSPI_1_DQ_3 J17 1000 -1000 200 L 50 50 4 1 B
X QSPI_1_DQ_1 J18 1000 -800 200 L 50 50 4 1 B
X QSPI_0_CS_0 J19 1000 -400 200 L 50 50 4 1 O
X QSPI_1_CS_3 J20 1000 -1400 200 L 50 50 4 1 O
X QSPI_0_DQ_2 J21 1000 -200 200 L 50 50 4 1 B
X QSPI_1_CS_0 K17 1000 -1100 200 L 50 50 4 1 O
X QSPI_0_SCK K18 1000 100 200 L 50 50 4 1 O
X I2C_0_SDA W13 -1000 -500 200 R 50 50 4 1 B
X UART_0_RXD W14 1000 1200 200 L 50 50 4 1 I
X QSPI_2_SCK W15 1000 800 200 L 50 50 4 1 O
X UART_0_TXD Y13 1000 1300 200 L 50 50 4 1 O
X I2C_0_SCL Y14 -1000 -400 200 R 50 50 4 1 B
X QSPI_2_DQ_3 Y15 1000 400 200 L 50 50 4 1 B
X HFXOSCIN A15 1100 -100 200 L 50 50 5 1 P
X PRCI_RSVD0 A16 -1100 1200 200 R 50 50 5 1 P
X PRCI_PORESET_N A17 -1100 -1200 200 R 50 50 5 1 I
X MSEL_MSEL_0 A19 1100 -900 200 L 50 50 5 1 I
X MSEL_MSEL_2 A20 1100 -1100 200 L 50 50 5 1 I
X HFXOSCOUT B15 1100 -400 200 L 50 50 5 1 P
X PRCI_RTCXALTCLKIN B16 -1100 1000 200 R 50 50 5 1 P
X PRCI_RSVD6 B17 -1100 200 200 R 50 50 5 1 P
X MSEL_MSEL_3 B19 1100 -1200 200 L 50 50 5 1 I
X PRCI_RSVD15 C14 1100 300 200 L 50 50 5 1 P
X PRCI_HFXSEL C15 -1100 -700 200 R 50 50 5 1 I
X PRCI_RSVD4 C16 -1100 400 200 R 50 50 5 1 P
X PRCI_ERESET_N C17 -1100 -900 200 R 50 50 5 1 I
X MSEL_MSEL_1 C18 1100 -1000 200 L 50 50 5 1 I
X JTAG_TDI C19 1100 900 200 L 50 50 5 1 I
X PRCI_RSVD1 D13 -1100 800 200 R 50 50 5 1 P
X PRCI_RSVD11 D14 -1100 -400 200 R 50 50 5 1 P
X PRCI_RTCXSEL D15 -1100 1100 200 R 50 50 5 1 I
X PRCI_RSVD3 D16 -1100 500 200 R 50 50 5 1 P
X PRCI_RSVD10 D17 -1100 -300 200 R 50 50 5 1 P
X JTAG_TCK D18 1100 1000 200 L 50 50 5 1 I
X PRCI_RSVD2 E13 -1100 700 200 R 50 50 5 1 P
X PRCI_RSVD12 E14 -1100 -500 200 R 50 50 5 1 P
X PRCI_RSVD5 E15 -1100 300 200 R 50 50 5 1 P
X PRCI_RSVD9 E16 -1100 -100 200 R 50 50 5 1 P
X JTAG_TDO E17 1100 800 200 L 50 50 5 1 O
X PRCI_RSVD14 F13 1100 400 200 L 50 50 5 1 P
X PRCI_RSVD13 F14 1100 500 200 L 50 50 5 1 P
X PRCI_HFXCLKIN F15 1100 100 200 L 50 50 5 1 I
X JTAG_TMS F16 1100 700 200 L 50 50 5 1 I
X PRCI_RSVD7 G13 -1100 100 200 R 50 50 5 1 P
X PRCI_RSVD8 H13 -1100 0 200 R 50 50 5 1 P
X VSS A1 -100 -900 200 U 50 50 6 1 W
X VSS A14 -100 -900 200 U 50 50 6 1 P N
X VSS A18 -100 -900 200 U 50 50 6 1 P N
X VSS A2 -100 -900 200 U 50 50 6 1 P N
X VSS A22 -100 -900 200 U 50 50 6 1 P N
X VSS A3 -100 -900 200 U 50 50 6 1 P N
X VSS A9 -100 -900 200 U 50 50 6 1 P N
X VDD AA17 -100 900 200 D 50 50 6 1 W
X VSS AA2 -100 -900 200 U 50 50 6 1 P N
X VSS AB1 -100 -900 200 U 50 50 6 1 P N
X VSS AB10 -100 -900 200 U 50 50 6 1 P N
X VSS AB13 -100 -900 200 U 50 50 6 1 P N
X VSS AB17 -100 -900 200 U 50 50 6 1 P N
X VSS AB22 -100 -900 200 U 50 50 6 1 P N
X VSS AB4 -100 -900 200 U 50 50 6 1 P N
X VSS AB7 -100 -900 200 U 50 50 6 1 P N
X VDD B14 -100 900 200 D 50 50 6 1 P N
X VDD B18 -100 900 200 D 50 50 6 1 P N
X VDD B9 -100 900 200 D 50 50 6 1 P N
X VSS D1 -100 -900 200 U 50 50 6 1 P N
X VSS D12 -100 -900 200 U 50 50 6 1 P N
X VDD E21 -100 900 200 D 50 50 6 1 P N
X VSS E22 -100 -900 200 U 50 50 6 1 P N
X VDD E3 -100 900 200 D 50 50 6 1 P N
X VSS E4 -100 -900 200 U 50 50 6 1 P N
X VSS F7 -100 -900 200 U 50 50 6 1 P N
X VSS G10 -100 -900 200 U 50 50 6 1 P N
X VDD G11 -100 900 200 D 50 50 6 1 P N
X VSS G12 -100 -900 200 U 50 50 6 1 P N
X OTP_VDD G14 600 900 200 D 50 50 6 1 W
X VDD G15 -100 900 200 D 50 50 6 1 P N
X VSS G16 -100 -900 200 U 50 50 6 1 P N
X VSS G2 -100 -900 200 U 50 50 6 1 P N
X VSS G6 -100 -900 200 U 50 50 6 1 P N
X DDR_VDDQ G7 100 900 200 D 50 50 6 1 W
X VSS G8 -100 -900 200 U 50 50 6 1 P N
X VDD G9 -100 900 200 D 50 50 6 1 P N
X VDD H10 -100 900 200 D 50 50 6 1 P N
X GIVSS H11 -300 -900 200 U 50 50 6 1 W
X VDD H12 -100 900 200 D 50 50 6 1 P N
X VDD H14 -100 900 200 D 50 50 6 1 P N
X VSS H15 -100 -900 200 U 50 50 6 1 P N
X VDD H16 -100 900 200 D 50 50 6 1 P N
X DDR_VDDQ H6 100 900 200 D 50 50 6 1 P N
X VSS H7 -100 -900 200 U 50 50 6 1 P N
X VDD H8 -100 900 200 D 50 50 6 1 P N
X VSS H9 -100 -900 200 U 50 50 6 1 P N
X VSS J1 -100 -900 200 U 50 50 6 1 P N
X VSS J10 -100 -900 200 U 50 50 6 1 P N
X GIVDD J11 -300 900 200 D 50 50 6 1 W
X GEMGXLPLL_AVSS J12 -400 -900 200 U 50 50 6 1 W
X DDRPLL_AVSS J13 400 -900 200 U 50 50 6 1 W
X COREPLL_AVSS J14 700 -900 200 U 50 50 6 1 W
X VDD J15 -100 900 200 D 50 50 6 1 P N
X VSS J16 -100 -900 200 U 50 50 6 1 P N
X VSS J22 -100 -900 200 U 50 50 6 1 P N
X VSS J6 -100 -900 200 U 50 50 6 1 P N
X DDR_VDDQ J7 100 900 200 D 50 50 6 1 P N
X VSS J8 -100 -900 200 U 50 50 6 1 P N
X VDD J9 -100 900 200 D 50 50 6 1 P N
X VDD K10 -100 900 200 D 50 50 6 1 P N
X VSS K11 -100 -900 200 U 50 50 6 1 P N
X GEMGXLPLL_AVDD K12 -400 900 200 D 50 50 6 1 W
X DDRPLL_AVDD K13 400 900 200 D 50 50 6 1 W
X COREPLL_AVDD K14 700 900 200 D 50 50 6 1 W
X IVSS K15 -600 -900 200 U 50 50 6 1 W
X IVDD K16 -600 900 200 D 50 50 6 1 W
X VDD K21 -100 900 200 D 50 50 6 1 P N
X DDR_VDDQ K6 100 900 200 D 50 50 6 1 P N
X VSS K7 -100 -900 200 U 50 50 6 1 P N
X VDD K8 -100 900 200 D 50 50 6 1 P N
X VSS K9 -100 -900 200 U 50 50 6 1 P N
X VSS L10 -100 -900 200 U 50 50 6 1 P N
X VDD L11 -100 900 200 D 50 50 6 1 P N
X VSS L12 -100 -900 200 U 50 50 6 1 P N
X VDD L13 -100 900 200 D 50 50 6 1 P N
X VSS L14 -100 -900 200 U 50 50 6 1 P N
X IVSS L15 -600 -900 200 U 50 50 6 1 P N
X IVDD L16 -600 900 200 D 50 50 6 1 P N
X VSS L6 -100 -900 200 U 50 50 6 1 P N
X DDR_VDDQ L7 100 900 200 D 50 50 6 1 P N
X VSS L8 -100 -900 200 U 50 50 6 1 P N
X DDR_VDDPLL L9 300 900 200 D 50 50 6 1 P N
X VDD M10 -100 900 200 D 50 50 6 1 P N
X VSS M11 -100 -900 200 U 50 50 6 1 P N
X VDD M12 -100 900 200 D 50 50 6 1 P N
X VSS M13 -100 -900 200 U 50 50 6 1 P N
X VDD M14 -100 900 200 D 50 50 6 1 P N
X IVSS M15 -600 -900 200 U 50 50 6 1 P N
X IVDD M16 -600 900 200 D 50 50 6 1 P N
X DDR_VDDQ M6 100 900 200 D 50 50 6 1 P N
X VSS M7 -100 -900 200 U 50 50 6 1 P N
X VDD M8 -100 900 200 D 50 50 6 1 P N
X DDR_VDDPLL M9 300 900 200 D 50 50 6 1 W
X VSS N10 -100 -900 200 U 50 50 6 1 P N
X VDD N11 -100 900 200 D 50 50 6 1 P N
X VSS N12 -100 -900 200 U 50 50 6 1 P N
X VDD N13 -100 900 200 D 50 50 6 1 P N
X VSS N14 -100 -900 200 U 50 50 6 1 P N
X IVSS N15 -600 -900 200 U 50 50 6 1 P N
X IVDD N16 -600 900 200 D 50 50 6 1 P N
X VSS N6 -100 -900 200 U 50 50 6 1 P N
X DDR_VDDQ N7 100 900 200 D 50 50 6 1 P N
X VSS N8 -100 -900 200 U 50 50 6 1 P N
X VDD N9 -100 900 200 D 50 50 6 1 P N
X VSS P1 -100 -900 200 U 50 50 6 1 P N
X VDD P10 -100 900 200 D 50 50 6 1 P N
X VSS P11 -100 -900 200 U 50 50 6 1 P N
X VDD P12 -100 900 200 D 50 50 6 1 P N
X VSS P13 -100 -900 200 U 50 50 6 1 P N
X VDD P14 -100 900 200 D 50 50 6 1 P N
X VSS P15 -100 -900 200 U 50 50 6 1 P N
X VDD P16 -100 900 200 D 50 50 6 1 P N
X VDD P2 -100 900 200 D 50 50 6 1 P N
X VDD P21 -100 900 200 D 50 50 6 1 P N
X VSS P22 -100 -900 200 U 50 50 6 1 P N
X DDR_VDDQ P6 100 900 200 D 50 50 6 1 P N
X VSS P7 -100 -900 200 U 50 50 6 1 P N
X VDD P8 -100 900 200 D 50 50 6 1 P N
X VSS P9 -100 -900 200 U 50 50 6 1 P N
X VSS R10 -100 -900 200 U 50 50 6 1 P N
X VDD R11 -100 900 200 D 50 50 6 1 P N
X VSS R12 -100 -900 200 U 50 50 6 1 P N
X VDD R13 -100 900 200 D 50 50 6 1 P N
X VSS R14 -100 -900 200 U 50 50 6 1 P N
X VDD R15 -100 900 200 D 50 50 6 1 P N
X VSS R16 -100 -900 200 U 50 50 6 1 P N
X VSS R6 -100 -900 200 U 50 50 6 1 P N
X DDR_VDDQ R7 100 900 200 D 50 50 6 1 P N
X VSS R8 -100 -900 200 U 50 50 6 1 P N
X VDD R9 -100 900 200 D 50 50 6 1 P N
X VDD T10 -100 900 200 D 50 50 6 1 P N
X VSS T11 -100 -900 200 U 50 50 6 1 P N
X VDD T12 -100 900 200 D 50 50 6 1 P N
X VSS T13 -100 -900 200 U 50 50 6 1 P N
X VDD T14 -100 900 200 D 50 50 6 1 P N
X VSS T15 -100 -900 200 U 50 50 6 1 P N
X VDD T16 -100 900 200 D 50 50 6 1 P N
X VSS T17 -100 -900 200 U 50 50 6 1 P N
X DDR_VDDQ T6 100 900 200 D 50 50 6 1 P N
X VSS T7 -100 -900 200 U 50 50 6 1 P N
X VDD T8 -100 900 200 D 50 50 6 1 P N
X VSS T9 -100 -900 200 U 50 50 6 1 P N
X VSS U10 -100 -900 200 U 50 50 6 1 P N
X VDD U11 -100 900 200 D 50 50 6 1 P N
X VSS U12 -100 -900 200 U 50 50 6 1 P N
X VDD U13 -100 900 200 D 50 50 6 1 P N
X VSS U14 -100 -900 200 U 50 50 6 1 P N
X VDD U15 -100 900 200 D 50 50 6 1 P N
X VSS U16 -100 -900 200 U 50 50 6 1 P N
X VSS U6 -100 -900 200 U 50 50 6 1 P N
X DDR_VDDQCK U7 200 900 200 D 50 50 6 1 W
X VSS U8 -100 -900 200 U 50 50 6 1 P N
X VDD U9 -100 900 200 D 50 50 6 1 P N
X VSS V1 -100 -900 200 U 50 50 6 1 P N
X VDD V10 -100 900 200 D 50 50 6 1 P N
X VSS V11 -100 -900 200 U 50 50 6 1 P N
X VDD V12 -100 900 200 D 50 50 6 1 P N
X VSS V13 -100 -900 200 U 50 50 6 1 P N
X VDD V14 -100 900 200 D 50 50 6 1 P N
X VSS V15 -100 -900 200 U 50 50 6 1 P N
X VDD V21 -100 900 200 D 50 50 6 1 P N
X VSS V22 -100 -900 200 U 50 50 6 1 P N
X VDD V6 -100 900 200 D 50 50 6 1 P N
X VSS V7 -100 -900 200 U 50 50 6 1 P N
X VDD V8 -100 900 200 D 50 50 6 1 P N
X VSS V9 -100 -900 200 U 50 50 6 1 P N
ENDDRAW
ENDDEF
#
#End Library