一个从零开始写的极简、非常易懂的RISC-V处理器核。
基于zynq的HDMI驱动,开发环境：Miz702开发板（兼容zedboard），vivado 2015.2
Icarus Verilog is intended to compile ALL of the Verilog HDL as
described in the IEEE-1364 standard. Of course, it's not quite there
yet. It does currently handle a mix of structural and behavioural
constructs. For a view of the current state of Icarus Verilog, see its
home page at <http://iverilog.icarus.com/>.
开源FPGA Lattice的iCE40系列芯片 入门教程
CPEN211LAB, make a RISCV computer
chiplab项目致力于构建基于LoongArch32 Reduced的soc敏捷开发平台
FPGA&VerilogHDL应用设计教程，包括课程思维导图、各章实例、各实验源码、综合实验例程。
玉衡是一款从零开始写的 RISC-V 内核的处理器，基于 Verilog 硬件设计语言实现，五级流水线设计，支持 RV32IM 指令集，支持中断，支持 RT-Thread Nano 3.1.5
