1 Star 1 Fork 7

pengchaochn / riscv-isa-sim

加入 Gitee
与超过 1200万 开发者一起发现、参与优秀开源项目,私有仓库也完全免费 :)
免费加入
克隆/下载
ChangeLog.md 966 Bytes
一键复制 编辑 原始数据 按行查看 历史

Version 1.0.1-dev

  • Preliminary support for a subset of the Vector Extension, v0.7.1.
  • Support S-mode vectored interrupts (i.e. stvec[0] is now writable).
  • Added support for dynamic linking of libraries containing MMIO devices.
  • Added --priv flag to control which privilege modes are available.
  • When the commit log is enabled at configure time (--enable-commitlog), it must also be enabled at runtime with the --log-commits option.
  • Several debug-related additions and changes:
    • Added hasel debug feature.
    • Added --dm-no-abstract-csr command-line option.
    • Added --dm-no-halt-groups command line option.
    • Renamed --progsize to --dm-progsize.
    • Renamed --debug-sba to --dm-sba.
    • Renamed --debug-auth to --dm-auth.
    • Renamed --abstract-rti to --dm-abstract-rti.
    • Renamed --without-hasel to --dm-no-hasel.

Version 1.0.0 (2019-03-30)

  • First versioned release.
C/C++
1
https://gitee.com/pengchaochn/riscv-isa-sim.git
git@gitee.com:pengchaochn/riscv-isa-sim.git
pengchaochn
riscv-isa-sim
riscv-isa-sim
master

搜索帮助