From c8d9886a22b145010c04704e6c6271fb71e1b631 Mon Sep 17 00:00:00 2001 From: liuhy Date: Fri, 7 May 2021 19:57:29 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E8=BD=AF=E4=BB=B6=E9=85=8D?= =?UTF-8?q?=E7=BD=AE=E7=9A=84=E6=8E=A5=E5=8F=A3=EF=BC=8C=E4=BC=98=E5=8C=96?= =?UTF-8?q?=E9=A9=B1=E5=8A=A8=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/essemi/es32f369x/.config | 90 +- bsp/essemi/es32f369x/drivers/ES/Kconfig | 197 + .../es32f369x/drivers/ES/es_conf_info_adc.h | 97 + .../es32f369x/drivers/ES/es_conf_info_can.h | 73 + .../es32f369x/drivers/ES/es_conf_info_cmu.h | 96 + .../es32f369x/drivers/ES/es_conf_info_gpio.h | 5157 +++++++++++++++++ .../drivers/ES/es_conf_info_hwtimer.h | 115 + .../es32f369x/drivers/ES/es_conf_info_i2c.h | 95 + .../es32f369x/drivers/ES/es_conf_info_map.h | 1764 ++++++ .../es32f369x/drivers/ES/es_conf_info_pm.h | 32 + .../es32f369x/drivers/ES/es_conf_info_pwm.h | 78 + .../es32f369x/drivers/ES/es_conf_info_rtc.h | 43 + .../drivers/ES/es_conf_info_select.h | 43 + .../es32f369x/drivers/ES/es_conf_info_spi.h | 159 + .../es32f369x/drivers/ES/es_conf_info_uart.h | 205 + bsp/essemi/es32f369x/drivers/Kconfig | 132 +- bsp/essemi/es32f369x/drivers/SConscript | 19 +- bsp/essemi/es32f369x/drivers/board.c | 93 +- bsp/essemi/es32f369x/drivers/board.h | 18 +- .../bsp_driver_example/adc_vol_sample.c | 6 + .../drivers/bsp_driver_example/can_sample.c | 6 +- .../bsp_driver_example/hwtimer_sample.c | 4 + .../drivers/bsp_driver_example/i2c_sample.c | 18 +- .../drivers/bsp_driver_example/pm_sample.c | 53 +- .../bsp_driver_example/pwm_led_sample.c | 9 +- .../drivers/bsp_driver_example/rtc_sample.c | 6 +- .../drivers/bsp_driver_example/spi_sample.c | 36 +- bsp/essemi/es32f369x/drivers/drv_adc.c | 129 +- bsp/essemi/es32f369x/drivers/drv_adc.h | 17 +- bsp/essemi/es32f369x/drivers/drv_can.c | 279 +- bsp/essemi/es32f369x/drivers/drv_can.h | 27 +- bsp/essemi/es32f369x/drivers/drv_gpio.c | 310 +- bsp/essemi/es32f369x/drivers/drv_gpio.h | 17 +- bsp/essemi/es32f369x/drivers/drv_hwtimer.c | 375 +- bsp/essemi/es32f369x/drivers/drv_hwtimer.h | 16 +- bsp/essemi/es32f369x/drivers/drv_i2c.c | 82 +- bsp/essemi/es32f369x/drivers/drv_i2c.h | 19 +- bsp/essemi/es32f369x/drivers/drv_pm.c | 60 +- bsp/essemi/es32f369x/drivers/drv_pm.h | 20 +- bsp/essemi/es32f369x/drivers/drv_pwm.c | 332 +- bsp/essemi/es32f369x/drivers/drv_rtc.c | 39 +- bsp/essemi/es32f369x/drivers/drv_rtc.h | 16 +- bsp/essemi/es32f369x/drivers/drv_spi.c | 212 +- bsp/essemi/es32f369x/drivers/drv_spi.h | 17 +- bsp/essemi/es32f369x/drivers/drv_uart.c | 448 +- bsp/essemi/es32f369x/drivers/drv_uart.h | 12 + .../EastSoft/ES32F36xx/Include/es32f36xx.h | 14 + .../ES32F36xx/Startup/gcc/startup_es32f36xx.S | 438 ++ .../Startup/keil/startup_es32f36xx.s | 14 + .../Include/ald_acmp.h | 14 + .../Include/ald_adc.h | 14 + .../Include/ald_bkpc.h | 14 + .../Include/ald_calc.h | 14 + .../Include/ald_can.h | 14 + .../Include/ald_cmu.h | 14 + .../Include/ald_conf.h | 14 + .../Include/ald_crc.h | 14 + .../Include/ald_crypt.h | 16 +- .../Include/ald_dac.h | 14 + .../Include/ald_dbgc.h | 15 + .../Include/ald_dma.h | 14 + .../Include/ald_ebi.h | 14 + .../Include/ald_flash.h | 14 + .../Include/ald_gpio.h | 16 +- .../Include/ald_i2c.h | 14 + .../Include/ald_i2s.h | 14 + .../Include/ald_iap.h | 14 + .../Include/ald_nand.h | 14 + .../Include/ald_nor_lcd.h | 14 + .../Include/ald_pis.h | 14 + .../Include/ald_pmu.h | 14 + .../Include/ald_qspi.h | 14 + .../Include/ald_rmu.h | 16 +- .../Include/ald_rtc.h | 14 + .../Include/ald_rtchw.h | 14 + .../Include/ald_spi.h | 14 + .../Include/ald_sram.h | 14 + .../Include/ald_syscfg.h | 14 + .../Include/ald_timer.h | 14 + .../Include/ald_trng.h | 16 +- .../Include/ald_tsense.h | 14 + .../Include/ald_uart.h | 16 +- .../Include/ald_usb.h | 16 +- .../Include/ald_wdt.h | 16 +- .../Include/type.h | 16 +- .../Include/utils.h | 14 + .../Source/ald_acmp.c | 14 + .../Source/ald_adc.c | 14 + .../Source/ald_bkpc.c | 14 + .../Source/ald_calc.c | 16 +- .../Source/ald_can.c | 14 + .../Source/ald_cmu.c | 16 +- .../Source/ald_crc.c | 14 + .../Source/ald_crypt.c | 14 + .../Source/ald_dac.c | 14 + .../Source/ald_dma.c | 14 + .../Source/ald_ebi.c | 14 + .../Source/ald_flash.c | 14 + .../Source/ald_flash_ext.c | 14 + .../Source/ald_gpio.c | 16 +- .../Source/ald_i2c.c | 14 + .../Source/ald_i2s.c | 14 + .../Source/ald_iap.c | 14 + .../Source/ald_nand.c | 14 + .../Source/ald_nor_lcd.c | 14 + .../Source/ald_pis.c | 14 + .../Source/ald_pmu.c | 14 + .../Source/ald_qspi.c | 14 + .../Source/ald_rmu.c | 14 + .../Source/ald_rtc.c | 14 + .../Source/ald_rtchw.c | 14 + .../Source/ald_spi.c | 14 + .../Source/ald_sram.c | 14 + .../Source/ald_timer.c | 14 + .../Source/ald_trng.c | 14 + .../Source/ald_tsense.c | 14 + .../Source/ald_uart.c | 14 + .../Source/ald_usb.c | 14 + .../Source/ald_wdt.c | 14 + .../Source/utils.c | 14 + bsp/essemi/es32f369x/project.uvoptx | 558 +- bsp/essemi/es32f369x/project.uvprojx | 356 +- bsp/essemi/es32f369x/rtconfig.h | 21 +- bsp/essemi/es32f369x/template.uvoptx | 8 +- bsp/essemi/es32f369x/template.uvprojx | 6 +- 125 files changed, 11970 insertions(+), 1533 deletions(-) create mode 100644 bsp/essemi/es32f369x/drivers/ES/Kconfig create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_adc.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_can.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_cmu.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_gpio.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_hwtimer.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_i2c.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_map.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_pm.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_pwm.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_rtc.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_select.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_spi.h create mode 100644 bsp/essemi/es32f369x/drivers/ES/es_conf_info_uart.h create mode 100644 bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S diff --git a/bsp/essemi/es32f369x/.config b/bsp/essemi/es32f369x/.config index af456dc765..5e47c69c47 100644 --- a/bsp/essemi/es32f369x/.config +++ b/bsp/essemi/es32f369x/.config @@ -19,8 +19,9 @@ CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_KSERVICE_USING_STDLIB is not set CONFIG_RT_DEBUG=y CONFIG_RT_DEBUG_COLOR=y # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -42,7 +43,7 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set +CONFIG_RT_USING_SIGNALS=y # # Memory Management @@ -52,6 +53,7 @@ CONFIG_RT_USING_MEMPOOL=y # CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -114,31 +116,21 @@ CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 -CONFIG_RT_USING_CAN=y -# CONFIG_RT_CAN_USING_HDR is not set -CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y -# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y -CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set -CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -CONFIG_RT_USING_PM=y -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set -# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_QSPI is not set -# CONFIG_RT_USING_SPI_MSD is not set -# CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -159,7 +151,7 @@ CONFIG_RT_USING_SPI=y # # CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_LIBC_USING_TIME is not set +CONFIG_RT_LIBC_USING_TIME=y # # Network @@ -305,6 +297,8 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set # CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set # # tools packages @@ -319,6 +313,7 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set # CONFIG_PKG_USING_NR_MICRO_SHELL is not set # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set @@ -326,6 +321,10 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_GPS_RMC is not set # CONFIG_PKG_USING_URLENCODE is not set # CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set # # system packages @@ -352,7 +351,16 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_RAMDISK is not set # CONFIG_PKG_USING_MININI is not set # CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_PPOOL is not set # @@ -408,6 +416,10 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set # # miscellaneous packages @@ -417,6 +429,7 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set @@ -437,17 +450,23 @@ CONFIG_RT_USING_SPI=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_NNOM is not set # CONFIG_PKG_USING_LIBANN is not set # CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# # CONFIG_PKG_USING_THREES is not set # CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_LWGPS is not set # CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set CONFIG_SOC_ES32F3696LT=y @@ -487,12 +506,13 @@ CONFIG_BSP_USING_UART0=y # # CAN Drivers # -# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_CAN0 is not set # # ADC Drivers # -# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_ADC0 is not set +# CONFIG_BSP_USING_ADC1 is not set # # RTC Drivers @@ -500,16 +520,26 @@ CONFIG_BSP_USING_UART0=y # CONFIG_BSP_USING_RTC is not set # -# HWtimer Drivers +# HWTIMER Drivers # -# CONFIG_BSP_USING_HWTIMER0 is not set -# CONFIG_BSP_USING_HWTIMER1 is not set +# CONFIG_BSP_USING_AD16C4T0_HWTIMER is not set +# CONFIG_BSP_USING_AD16C4T1_HWTIMER is not set +# CONFIG_BSP_USING_GP32C4T0_HWTIMER is not set +# CONFIG_BSP_USING_GP32C4T1_HWTIMER is not set +# CONFIG_BSP_USING_GP16C4T0_HWTIMER is not set +# CONFIG_BSP_USING_GP16C4T1_HWTIMER is not set +# CONFIG_BSP_USING_BS16T0_HWTIMER is not set +# CONFIG_BSP_USING_BS16T1_HWTIMER is not set # # PWM Drivers # -# CONFIG_BSP_USING_PWM0 is not set -# CONFIG_BSP_USING_PWM1 is not set +# CONFIG_BSP_USING_AD16C4T0_PWM is not set +# CONFIG_BSP_USING_AD16C4T1_PWM is not set +# CONFIG_BSP_USING_GP32C4T0_PWM is not set +# CONFIG_BSP_USING_GP32C4T1_PWM is not set +# CONFIG_BSP_USING_GP16C4T0_PWM is not set +# CONFIG_BSP_USING_GP16C4T1_PWM is not set # # PM Drivers diff --git a/bsp/essemi/es32f369x/drivers/ES/Kconfig b/bsp/essemi/es32f369x/drivers/ES/Kconfig new file mode 100644 index 0000000000..9ba55d110e --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/Kconfig @@ -0,0 +1,197 @@ +menu "UART Drivers" + + config BSP_USING_UART0 + bool "Register UART0 " + select RT_USING_SERIAL + default y + + config BSP_USING_UART1 + bool "Register UART1 " + select RT_USING_SERIAL + default n + + config BSP_USING_UART2 + bool "Register UART2 " + select RT_USING_SERIAL + default n + + config BSP_USING_UART3 + bool "Register UART3 " + select RT_USING_SERIAL + default n + + config BSP_USING_UART4 + bool "Register UART4 " + select RT_USING_SERIAL + default n + + config BSP_USING_UART5 + bool "Register UART5 " + select RT_USING_SERIAL + default n + +endmenu + +menu "SPI Drivers" + + config BSP_USING_SPI0 + bool "Register SPI0 " + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI1 + bool "Register SPI1 " + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI2 + bool "Register SPI2 " + select RT_USING_SPI + select RT_USING_PIN + default n + +endmenu + +menu "I2C Drivers" + + config BSP_USING_I2C0 + bool "Register I2C0 " + select RT_USING_I2C + default n + + config BSP_USING_I2C1 + bool "Register I2C1 " + select RT_USING_I2C + default n + +endmenu + +menu "CAN Drivers" + + config BSP_USING_CAN0 + bool "Register CAN0 " + select RT_USING_CAN + select RT_CAN_USING_HDR + select BSP_USING_CAN + default n + +endmenu + +menu "ADC Drivers" + + config BSP_USING_ADC0 + bool "Register ADC0 " + select RT_USING_ADC + default n + + config BSP_USING_ADC1 + bool "Register ADC1 " + select RT_USING_ADC + default n + +endmenu + +menu "RTC Drivers" + + config BSP_USING_RTC + bool "Register RTC " + select RT_USING_RTC + default n + +endmenu + +menu "HWTIMER Drivers" + + config BSP_USING_AD16C4T0_HWTIMER + bool "Register HWTIMER0 " + select RT_USING_HWTIMER + default n + + config BSP_USING_AD16C4T1_HWTIMER + bool "Register HWTIMER1 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP32C4T0_HWTIMER + bool "Register HWTIMER2 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP32C4T1_HWTIMER + bool "Register HWTIMER3 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP16C4T0_HWTIMER + bool "Register HWTIMER4 " + select RT_USING_HWTIMER + default n + + config BSP_USING_GP16C4T1_HWTIMER + bool "Register HWTIMER5 " + select RT_USING_HWTIMER + default n + + config BSP_USING_BS16T0_HWTIMER + bool "Register HWTIMER6 " + select RT_USING_HWTIMER + default n + + config BSP_USING_BS16T1_HWTIMER + bool "Register HWTIMER7 " + select RT_USING_HWTIMER + default n + +endmenu + +menu "PWM Drivers" + + config BSP_USING_AD16C4T0_PWM + bool "Register PWM0 " + select RT_USING_PWM + default n + depends on !BSP_USING_AD16C4T0_HWTIMER + + config BSP_USING_AD16C4T1_PWM + bool "Register PWM1 " + select RT_USING_PWM + default n + depends on !BSP_USING_AD16C4T1_HWTIMER + + config BSP_USING_GP32C4T0_PWM + bool "Register PWM2 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP32C4T0_HWTIMER + + config BSP_USING_GP32C4T1_PWM + bool "Register PWM3 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP32C4T1_HWTIMER + + config BSP_USING_GP16C4T0_PWM + bool "Register PWM4 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP16C4T0_HWTIMER + + config BSP_USING_GP16C4T1_PWM + bool "Register PWM5 " + select RT_USING_PWM + default n + depends on !BSP_USING_GP16C4T1_HWTIMER + +endmenu + +menu "PM Drivers" + + config BSP_USING_PM + bool "Register PM " + select RT_USING_PM + default n + +endmenu + diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_adc.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_adc.h new file mode 100644 index 0000000000..772f7a0df0 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_adc.h @@ -0,0 +1,97 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_ADC_H__ +#define __ES_CONF_INFO_ADC_H__ + +#include "es_conf_info_map.h" + +#include + + +#define ES_C_ADC_CLK_DIV_1 ADC_CKDIV_1 +#define ES_C_ADC_CLK_DIV_2 ADC_CKDIV_2 +#define ES_C_ADC_CLK_DIV_4 ADC_CKDIV_4 +#define ES_C_ADC_CLK_DIV_8 ADC_CKDIV_8 +#define ES_C_ADC_CLK_DIV_16 ADC_CKDIV_16 +#define ES_C_ADC_CLK_DIV_32 ADC_CKDIV_32 +#define ES_C_ADC_CLK_DIV_64 ADC_CKDIV_64 +#define ES_C_ADC_CLK_DIV_128 ADC_CKDIV_128 + +#define ES_C_ADC_ALIGN_RIGHT ADC_DATAALIGN_RIGHT +#define ES_C_ADC_ALIGN_LEFT ADC_DATAALIGN_LEFT + +#define ES_C_ADC_CONV_BIT_6 ADC_CONV_BIT_6 +#define ES_C_ADC_CONV_BIT_8 ADC_CONV_BIT_8 +#define ES_C_ADC_CONV_BIT_10 ADC_CONV_BIT_10 +#define ES_C_ADC_CONV_BIT_12 ADC_CONV_BIT_12 + +#define ES_C_ADC_SAMPLE_TIME_1 ADC_SAMPLETIME_1 +#define ES_C_ADC_SAMPLE_TIME_2 ADC_SAMPLETIME_2 +#define ES_C_ADC_SAMPLE_TIME_4 ADC_SAMPLETIME_4 +#define ES_C_ADC_SAMPLE_TIME_15 ADC_SAMPLETIME_15 + +/* ADC 配置 */ + +/* codes_main */ + + +#define ES_ADC0_ALIGN ES_C_ADC_ALIGN_RIGHT +#define ES_ADC1_ALIGN ES_C_ADC_ALIGN_RIGHT +#define ES_ADC1_DATA_BIT ES_C_ADC_CONV_BIT_12 +#define ES_ADC0_DATA_BIT ES_C_ADC_CONV_BIT_12 + +#ifndef ES_DEVICE_NAME_ADC0 +#define ES_DEVICE_NAME_ADC0 "adc0" +#endif +#ifndef ES_DEVICE_NAME_ADC1 +#define ES_DEVICE_NAME_ADC1 "adc1" +#endif + +#ifndef ES_ADC0_CLK_DIV +#define ES_ADC0_CLK_DIV ES_C_ADC_CLK_DIV_128 +#endif +#ifndef ES_ADC0_ALIGN +#define ES_ADC0_ALIGN ES_C_ADC_ALIGN_RIGHT +#endif +#ifndef ES_ADC0_DATA_BIT +#define ES_ADC0_DATA_BIT ES_C_ADC_CONV_BIT_12 +#endif +#ifndef ES_ADC0_NCH_SAMPLETIME +#define ES_ADC0_NCH_SAMPLETIME ES_C_ADC_SAMPLE_TIME_4 +#endif + +#ifndef ES_ADC1_CLK_DIV +#define ES_ADC1_CLK_DIV ES_C_ADC_CLK_DIV_128 +#endif +#ifndef ES_ADC1_ALIGN +#define ES_ADC1_ALIGN ES_C_ADC_ALIGN_RIGHT +#endif +#ifndef ES_ADC1_DATA_BIT +#define ES_ADC1_DATA_BIT ES_C_ADC_CONV_BIT_12 +#endif +#ifndef ES_ADC1_NCH_SAMPLETIME +#define ES_ADC1_NCH_SAMPLETIME ES_C_ADC_SAMPLE_TIME_4 +#endif + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_can.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_can.h new file mode 100644 index 0000000000..46df1ed054 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_can.h @@ -0,0 +1,73 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_CAN_H__ +#define __ES_CONF_INFO_CAN_H__ + +#include "es_conf_info_map.h" +#include +#include + + +/*默认的CAN硬件过滤器的编号 0 */ +#define ES_C_CAN_DEFAULT_FILTER_NUMBER 0 + +/*硬件过滤器，过滤帧类型*/ +#define ES_C_CAN_FILTER_FRAME_TYPE 0 + + +#define ES_C_CAN_SJW_NUM_1 CAN_SJW_1 +#define ES_C_CAN_SJW_NUM_2 CAN_SJW_2 +#define ES_C_CAN_SJW_NUM_3 CAN_SJW_3 +#define ES_C_CAN_SJW_NUM_4 CAN_SJW_4 + + + +/* CAN 配置 */ + +/* codes_main */ + + + +#ifndef ES_DEVICE_NAME_CAN0 +#define ES_DEVICE_NAME_CAN0 "can0" +#endif + +#ifndef ES_CAN0_AUTO_BAN_RE_T +#define ES_CAN0_AUTO_BAN_RE_T ES_C_ENABLE +#endif +#ifndef ES_CAN0_SPEED +#define ES_CAN0_SPEED 1000000 +#endif +#ifndef ES_CAN0_SJW +#define ES_CAN0_SJW ES_C_CAN_SJW_NUM_4 +#endif + +#define ES_CAN0_CONFIG \ +{ \ + ES_CAN0_SPEED, \ + RT_CANMSG_BOX_SZ, \ + RT_CANSND_BOX_NUM, \ + RT_CAN_MODE_NORMAL, \ +}; +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_cmu.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_cmu.h new file mode 100644 index 0000000000..90f4453f60 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_cmu.h @@ -0,0 +1,96 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_CMU_H__ +#define __ES_CONF_INFO_CMU_H__ + + +#include + + +/* 时钟树 配置 */ + +#define ES_C_MUL_9 CMU_PLL1_OUTPUT_36M +#define ES_C_MUL_12 CMU_PLL1_OUTPUT_48M +#define ES_C_MUL_18 CMU_PLL1_OUTPUT_72M +#define ES_C_MUL_24 CMU_PLL1_OUTPUT_96M + +#define ES_C_DIV_1 CMU_DIV_1 +#define ES_C_DIV_2 CMU_DIV_2 +#define ES_C_DIV_4 CMU_DIV_4 +#define ES_C_DIV_8 CMU_DIV_8 +#define ES_C_DIV_16 CMU_DIV_16 +#define ES_C_DIV_32 CMU_DIV_32 +#define ES_C_DIV_64 CMU_DIV_64 +#define ES_C_DIV_128 CMU_DIV_128 +#define ES_C_DIV_256 CMU_DIV_256 +#define ES_C_DIV_512 CMU_DIV_512 +#define ES_C_DIV_1024 CMU_DIV_1024 +#define ES_C_DIV_2048 CMU_DIV_2048 +#define ES_C_DIV_4096 CMU_DIV_4096 + +#define ES_C_HOSC_DIV_1 CMU_PLL1_INPUT_HOSC +#define ES_C_HOSC_DIV_2 CMU_PLL1_INPUT_HOSC_2 +#define ES_C_HOSC_DIV_3 CMU_PLL1_INPUT_HOSC_3 +#define ES_C_HOSC_DIV_4 CMU_PLL1_INPUT_HOSC_4 +#define ES_C_HOSC_DIV_5 CMU_PLL1_INPUT_HOSC_5 +#define ES_C_HOSC_DIV_6 CMU_PLL1_INPUT_HOSC_6 +#define ES_C_HRC_DIV_6 CMU_PLL1_INPUT_HRC_6 + + + + + +#define ES_PLL1_REFER_CLK ES_C_HOSC_DIV_3 +#define ES_PLL1_OUT_CLK ES_C_MUL_24 +#define ES_CMU_PLL1_EN ES_C_ENABLE +#define ES_CMU_PLL1_SAFE_EN ES_C_DISABLE +#define ES_CMU_LOSC_EN ES_C_ENABLE +#define ES_CMU_LRC_EN ES_C_ENABLE +#define ES_CMU_HOSC_EN ES_C_ENABLE +#define ES_CMU_HRC_EN ES_C_ENABLE +#define ES_CMU_SYS_DIV ES_C_DIV_1 +#define ES_CMU_HCLK_1_DIV ES_C_DIV_2 +#define ES_CMU_HCLK_2_DIV ES_C_DIV_2 +#define ES_CMU_PCLK_1_DIV ES_C_DIV_2 +#define ES_CMU_PCLK_2_DIV ES_C_DIV_4 +#define ES_CMU_UART_BUAND_MAX XXXXXX +#define ES_CMU_UART_BUAND_MIN XXXXXX +#define ES_CMU_SPI_BUAND_MAX XXXXXX +#define ES_CMU_SPI_BUAND_MIN XXXXXX +#define ES_CMU_CAN_BUAND_MAX XXXXXX +#define ES_SYS_CLK_SOURSE CMU_CLOCK_PLL1 +#define ES_PLL_CLK 96000000 +#define ES_SYS_SOURCE_CLK 96000000 +#define ES_SYS_CLK 96000000 +#define ES_PCLK1_CLK 48000000 +#define ES_PCLK2_CLK 24000000 +#define ES_HCLK1_CLK 48000000 +#define ES_HCLK2_CLK 48000000 +#define ES_CMU_EXTERN_CLK_LOSC 32768 +#define ES_CMU_EXTERN_CLK_HOSC 12000000 + + + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_gpio.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_gpio.h new file mode 100644 index 0000000000..7748e5fda2 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_gpio.h @@ -0,0 +1,5157 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_GPIO_H__ +#define __ES_CONF_INFO_GPIO_H__ + +#include "es_conf_info_map.h" + +#include +#include +#include + +/* GPIO 配置 */ + +typedef struct { + uint8_t pin; + uint8_t pin_mode; + uint8_t pin_level; + uint8_t irq_en; + uint8_t irq_mode; + void (*callback)(void *arg); +} gpio_conf_t; + +/*参数的定义*/ + +#define ES_C_GPIO_LEVEL_HIGH PIN_HIGH +#define ES_C_GPIO_LEVEL_LOW PIN_LOW + +#define ES_C_GPIO_MODE_OUTPUT PIN_MODE_OUTPUT +#define ES_C_GPIO_MODE_INPUT PIN_MODE_INPUT +#define ES_C_GPIO_MODE_INPUT_PULLUP PIN_MODE_INPUT_PULLUP +#define ES_C_GPIO_MODE_INPUT_PULLDOWN PIN_MODE_INPUT_PULLDOWN +#define ES_C_GPIO_MODE_OUTPUT_OD PIN_MODE_OUTPUT_OD + +#define ES_C_GPIO_IRQ_ENABLE PIN_IRQ_ENABLE +#define ES_C_GPIO_IRQ_DISABLE PIN_IRQ_DISABLE + +#define ES_C_GPIO_IRQ_MODE_FALL PIN_IRQ_MODE_FALLING +#define ES_C_GPIO_IRQ_MODE_RISE PIN_IRQ_MODE_RISING +#define ES_C_GPIO_IRQ_MODE_R_F PIN_IRQ_MODE_RISING_FALLING + + + + + +/* codes_main */ + + + + +#ifndef ES_DEVICE_NAME_PIN +#define ES_DEVICE_NAME_PIN "pin" +#endif + +/*GPIO外部中断回调函数控制需要，补充是否中断*/ +#if 11111 + +#ifndef ES_INIT_GPIO_A_0_IRQ_EN +#define ES_INIT_GPIO_A_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_1_IRQ_EN +#define ES_INIT_GPIO_A_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_2_IRQ_EN +#define ES_INIT_GPIO_A_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_3_IRQ_EN +#define ES_INIT_GPIO_A_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_4_IRQ_EN +#define ES_INIT_GPIO_A_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_5_IRQ_EN +#define ES_INIT_GPIO_A_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_6_IRQ_EN +#define ES_INIT_GPIO_A_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_7_IRQ_EN +#define ES_INIT_GPIO_A_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_8_IRQ_EN +#define ES_INIT_GPIO_A_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_9_IRQ_EN +#define ES_INIT_GPIO_A_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_10_IRQ_EN +#define ES_INIT_GPIO_A_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_11_IRQ_EN +#define ES_INIT_GPIO_A_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_12_IRQ_EN +#define ES_INIT_GPIO_A_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_13_IRQ_EN +#define ES_INIT_GPIO_A_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_14_IRQ_EN +#define ES_INIT_GPIO_A_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_A_15_IRQ_EN +#define ES_INIT_GPIO_A_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_0_IRQ_EN +#define ES_INIT_GPIO_B_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_1_IRQ_EN +#define ES_INIT_GPIO_B_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_2_IRQ_EN +#define ES_INIT_GPIO_B_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_3_IRQ_EN +#define ES_INIT_GPIO_B_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_4_IRQ_EN +#define ES_INIT_GPIO_B_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_5_IRQ_EN +#define ES_INIT_GPIO_B_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_6_IRQ_EN +#define ES_INIT_GPIO_B_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_7_IRQ_EN +#define ES_INIT_GPIO_B_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_8_IRQ_EN +#define ES_INIT_GPIO_B_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_9_IRQ_EN +#define ES_INIT_GPIO_B_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_10_IRQ_EN +#define ES_INIT_GPIO_B_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_11_IRQ_EN +#define ES_INIT_GPIO_B_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_12_IRQ_EN +#define ES_INIT_GPIO_B_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_13_IRQ_EN +#define ES_INIT_GPIO_B_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_14_IRQ_EN +#define ES_INIT_GPIO_B_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_B_15_IRQ_EN +#define ES_INIT_GPIO_B_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_0_IRQ_EN +#define ES_INIT_GPIO_C_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_1_IRQ_EN +#define ES_INIT_GPIO_C_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_2_IRQ_EN +#define ES_INIT_GPIO_C_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_3_IRQ_EN +#define ES_INIT_GPIO_C_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_4_IRQ_EN +#define ES_INIT_GPIO_C_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_5_IRQ_EN +#define ES_INIT_GPIO_C_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_6_IRQ_EN +#define ES_INIT_GPIO_C_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_7_IRQ_EN +#define ES_INIT_GPIO_C_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_8_IRQ_EN +#define ES_INIT_GPIO_C_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_9_IRQ_EN +#define ES_INIT_GPIO_C_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_10_IRQ_EN +#define ES_INIT_GPIO_C_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_11_IRQ_EN +#define ES_INIT_GPIO_C_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_12_IRQ_EN +#define ES_INIT_GPIO_C_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_13_IRQ_EN +#define ES_INIT_GPIO_C_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_14_IRQ_EN +#define ES_INIT_GPIO_C_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_C_15_IRQ_EN +#define ES_INIT_GPIO_C_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_0_IRQ_EN +#define ES_INIT_GPIO_D_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_1_IRQ_EN +#define ES_INIT_GPIO_D_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_2_IRQ_EN +#define ES_INIT_GPIO_D_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_3_IRQ_EN +#define ES_INIT_GPIO_D_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_4_IRQ_EN +#define ES_INIT_GPIO_D_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_5_IRQ_EN +#define ES_INIT_GPIO_D_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_6_IRQ_EN +#define ES_INIT_GPIO_D_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_7_IRQ_EN +#define ES_INIT_GPIO_D_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_8_IRQ_EN +#define ES_INIT_GPIO_D_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_9_IRQ_EN +#define ES_INIT_GPIO_D_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_10_IRQ_EN +#define ES_INIT_GPIO_D_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_11_IRQ_EN +#define ES_INIT_GPIO_D_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_12_IRQ_EN +#define ES_INIT_GPIO_D_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_13_IRQ_EN +#define ES_INIT_GPIO_D_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_14_IRQ_EN +#define ES_INIT_GPIO_D_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_D_15_IRQ_EN +#define ES_INIT_GPIO_D_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_0_IRQ_EN +#define ES_INIT_GPIO_E_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_1_IRQ_EN +#define ES_INIT_GPIO_E_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_2_IRQ_EN +#define ES_INIT_GPIO_E_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_3_IRQ_EN +#define ES_INIT_GPIO_E_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_4_IRQ_EN +#define ES_INIT_GPIO_E_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_5_IRQ_EN +#define ES_INIT_GPIO_E_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_6_IRQ_EN +#define ES_INIT_GPIO_E_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_7_IRQ_EN +#define ES_INIT_GPIO_E_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_8_IRQ_EN +#define ES_INIT_GPIO_E_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_9_IRQ_EN +#define ES_INIT_GPIO_E_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_10_IRQ_EN +#define ES_INIT_GPIO_E_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_11_IRQ_EN +#define ES_INIT_GPIO_E_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_12_IRQ_EN +#define ES_INIT_GPIO_E_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_13_IRQ_EN +#define ES_INIT_GPIO_E_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_14_IRQ_EN +#define ES_INIT_GPIO_E_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_E_15_IRQ_EN +#define ES_INIT_GPIO_E_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_0_IRQ_EN +#define ES_INIT_GPIO_F_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_1_IRQ_EN +#define ES_INIT_GPIO_F_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_2_IRQ_EN +#define ES_INIT_GPIO_F_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_3_IRQ_EN +#define ES_INIT_GPIO_F_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_4_IRQ_EN +#define ES_INIT_GPIO_F_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_5_IRQ_EN +#define ES_INIT_GPIO_F_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_6_IRQ_EN +#define ES_INIT_GPIO_F_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_7_IRQ_EN +#define ES_INIT_GPIO_F_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_8_IRQ_EN +#define ES_INIT_GPIO_F_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_9_IRQ_EN +#define ES_INIT_GPIO_F_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_10_IRQ_EN +#define ES_INIT_GPIO_F_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_11_IRQ_EN +#define ES_INIT_GPIO_F_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_12_IRQ_EN +#define ES_INIT_GPIO_F_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_13_IRQ_EN +#define ES_INIT_GPIO_F_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_14_IRQ_EN +#define ES_INIT_GPIO_F_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_F_15_IRQ_EN +#define ES_INIT_GPIO_F_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_0_IRQ_EN +#define ES_INIT_GPIO_G_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_1_IRQ_EN +#define ES_INIT_GPIO_G_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_2_IRQ_EN +#define ES_INIT_GPIO_G_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_3_IRQ_EN +#define ES_INIT_GPIO_G_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_4_IRQ_EN +#define ES_INIT_GPIO_G_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_5_IRQ_EN +#define ES_INIT_GPIO_G_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_6_IRQ_EN +#define ES_INIT_GPIO_G_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_7_IRQ_EN +#define ES_INIT_GPIO_G_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_8_IRQ_EN +#define ES_INIT_GPIO_G_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_9_IRQ_EN +#define ES_INIT_GPIO_G_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_10_IRQ_EN +#define ES_INIT_GPIO_G_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_11_IRQ_EN +#define ES_INIT_GPIO_G_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_12_IRQ_EN +#define ES_INIT_GPIO_G_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_13_IRQ_EN +#define ES_INIT_GPIO_G_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_14_IRQ_EN +#define ES_INIT_GPIO_G_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_G_15_IRQ_EN +#define ES_INIT_GPIO_G_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_0_IRQ_EN +#define ES_INIT_GPIO_H_0_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_1_IRQ_EN +#define ES_INIT_GPIO_H_1_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_2_IRQ_EN +#define ES_INIT_GPIO_H_2_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_3_IRQ_EN +#define ES_INIT_GPIO_H_3_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_4_IRQ_EN +#define ES_INIT_GPIO_H_4_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_5_IRQ_EN +#define ES_INIT_GPIO_H_5_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_6_IRQ_EN +#define ES_INIT_GPIO_H_6_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_7_IRQ_EN +#define ES_INIT_GPIO_H_7_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_8_IRQ_EN +#define ES_INIT_GPIO_H_8_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_9_IRQ_EN +#define ES_INIT_GPIO_H_9_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_10_IRQ_EN +#define ES_INIT_GPIO_H_10_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_11_IRQ_EN +#define ES_INIT_GPIO_H_11_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_12_IRQ_EN +#define ES_INIT_GPIO_H_12_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_13_IRQ_EN +#define ES_INIT_GPIO_H_13_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_14_IRQ_EN +#define ES_INIT_GPIO_H_14_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#ifndef ES_INIT_GPIO_H_15_IRQ_EN +#define ES_INIT_GPIO_H_15_IRQ_EN ES_C_GPIO_IRQ_DISABLE +#endif + +#endif //11111 + + + +/*是否需要 GPIO外部中断回调函数 （控制函数本体+声明）*/ +#if 11111 + +#if (ES_INIT_GPIO_A_0_IRQ_EN)||(ES_INIT_GPIO_B_0_IRQ_EN)||(ES_INIT_GPIO_C_0_IRQ_EN)||(ES_INIT_GPIO_D_0_IRQ_EN)|| \ + (ES_INIT_GPIO_E_0_IRQ_EN)||(ES_INIT_GPIO_F_0_IRQ_EN)||(ES_INIT_GPIO_G_0_IRQ_EN)||(ES_INIT_GPIO_H_0_IRQ_EN) +#define ES_CONF_EXTI_IRQ_0 +#endif + +#if (ES_INIT_GPIO_A_1_IRQ_EN)||(ES_INIT_GPIO_B_1_IRQ_EN)||(ES_INIT_GPIO_C_1_IRQ_EN)||(ES_INIT_GPIO_D_1_IRQ_EN)|| \ + (ES_INIT_GPIO_E_1_IRQ_EN)||(ES_INIT_GPIO_F_1_IRQ_EN)||(ES_INIT_GPIO_G_1_IRQ_EN)||(ES_INIT_GPIO_H_1_IRQ_EN) +#define ES_CONF_EXTI_IRQ_1 +#endif + +#if (ES_INIT_GPIO_A_2_IRQ_EN)||(ES_INIT_GPIO_B_2_IRQ_EN)||(ES_INIT_GPIO_C_2_IRQ_EN)||(ES_INIT_GPIO_D_2_IRQ_EN)|| \ + (ES_INIT_GPIO_E_2_IRQ_EN)||(ES_INIT_GPIO_F_2_IRQ_EN)||(ES_INIT_GPIO_G_2_IRQ_EN)||(ES_INIT_GPIO_H_2_IRQ_EN) +#define ES_CONF_EXTI_IRQ_2 +#endif + +#if (ES_INIT_GPIO_A_3_IRQ_EN)||(ES_INIT_GPIO_B_3_IRQ_EN)||(ES_INIT_GPIO_C_3_IRQ_EN)||(ES_INIT_GPIO_D_3_IRQ_EN)|| \ + (ES_INIT_GPIO_E_3_IRQ_EN)||(ES_INIT_GPIO_F_3_IRQ_EN)||(ES_INIT_GPIO_G_3_IRQ_EN)||(ES_INIT_GPIO_H_3_IRQ_EN) +#define ES_CONF_EXTI_IRQ_3 +#endif + +#if (ES_INIT_GPIO_A_4_IRQ_EN)||(ES_INIT_GPIO_B_4_IRQ_EN)||(ES_INIT_GPIO_C_4_IRQ_EN)||(ES_INIT_GPIO_D_4_IRQ_EN)|| \ + (ES_INIT_GPIO_E_4_IRQ_EN)||(ES_INIT_GPIO_F_4_IRQ_EN)||(ES_INIT_GPIO_G_4_IRQ_EN)||(ES_INIT_GPIO_H_4_IRQ_EN) +#define ES_CONF_EXTI_IRQ_4 +#endif + +#if (ES_INIT_GPIO_A_5_IRQ_EN)||(ES_INIT_GPIO_B_5_IRQ_EN)||(ES_INIT_GPIO_C_5_IRQ_EN)||(ES_INIT_GPIO_D_5_IRQ_EN)|| \ + (ES_INIT_GPIO_E_5_IRQ_EN)||(ES_INIT_GPIO_F_5_IRQ_EN)||(ES_INIT_GPIO_G_5_IRQ_EN)||(ES_INIT_GPIO_H_5_IRQ_EN) +#define ES_CONF_EXTI_IRQ_5 +#endif + +#if (ES_INIT_GPIO_A_6_IRQ_EN)||(ES_INIT_GPIO_B_6_IRQ_EN)||(ES_INIT_GPIO_C_6_IRQ_EN)||(ES_INIT_GPIO_D_6_IRQ_EN)|| \ + (ES_INIT_GPIO_E_6_IRQ_EN)||(ES_INIT_GPIO_F_6_IRQ_EN)||(ES_INIT_GPIO_G_6_IRQ_EN)||(ES_INIT_GPIO_H_6_IRQ_EN) +#define ES_CONF_EXTI_IRQ_6 +#endif + +#if (ES_INIT_GPIO_A_7_IRQ_EN)||(ES_INIT_GPIO_B_7_IRQ_EN)||(ES_INIT_GPIO_C_7_IRQ_EN)||(ES_INIT_GPIO_D_7_IRQ_EN)|| \ + (ES_INIT_GPIO_E_7_IRQ_EN)||(ES_INIT_GPIO_F_7_IRQ_EN)||(ES_INIT_GPIO_G_7_IRQ_EN)||(ES_INIT_GPIO_H_7_IRQ_EN) +#define ES_CONF_EXTI_IRQ_7 +#endif + +#if (ES_INIT_GPIO_A_8_IRQ_EN)||(ES_INIT_GPIO_B_8_IRQ_EN)||(ES_INIT_GPIO_C_8_IRQ_EN)||(ES_INIT_GPIO_D_8_IRQ_EN)|| \ + (ES_INIT_GPIO_E_8_IRQ_EN)||(ES_INIT_GPIO_F_8_IRQ_EN)||(ES_INIT_GPIO_G_8_IRQ_EN)||(ES_INIT_GPIO_H_8_IRQ_EN) +#define ES_CONF_EXTI_IRQ_8 +#endif + +#if (ES_INIT_GPIO_A_9_IRQ_EN)||(ES_INIT_GPIO_B_9_IRQ_EN)||(ES_INIT_GPIO_C_9_IRQ_EN)||(ES_INIT_GPIO_D_9_IRQ_EN)|| \ + (ES_INIT_GPIO_E_9_IRQ_EN)||(ES_INIT_GPIO_F_9_IRQ_EN)||(ES_INIT_GPIO_G_9_IRQ_EN)||(ES_INIT_GPIO_H_9_IRQ_EN) +#define ES_CONF_EXTI_IRQ_9 +#endif + +#if (ES_INIT_GPIO_A_10_IRQ_EN)||(ES_INIT_GPIO_B_10_IRQ_EN)||(ES_INIT_GPIO_C_10_IRQ_EN)||(ES_INIT_GPIO_D_10_IRQ_EN)|| \ + (ES_INIT_GPIO_E_10_IRQ_EN)||(ES_INIT_GPIO_F_10_IRQ_EN)||(ES_INIT_GPIO_G_10_IRQ_EN)||(ES_INIT_GPIO_H_10_IRQ_EN) +#define ES_CONF_EXTI_IRQ_10 +#endif + +#if (ES_INIT_GPIO_A_11_IRQ_EN)||(ES_INIT_GPIO_B_11_IRQ_EN)||(ES_INIT_GPIO_C_11_IRQ_EN)||(ES_INIT_GPIO_D_11_IRQ_EN)|| \ + (ES_INIT_GPIO_E_11_IRQ_EN)||(ES_INIT_GPIO_F_11_IRQ_EN)||(ES_INIT_GPIO_G_11_IRQ_EN)||(ES_INIT_GPIO_H_11_IRQ_EN) +#define ES_CONF_EXTI_IRQ_11 +#endif + +#if (ES_INIT_GPIO_A_12_IRQ_EN)||(ES_INIT_GPIO_B_12_IRQ_EN)||(ES_INIT_GPIO_C_12_IRQ_EN)||(ES_INIT_GPIO_D_12_IRQ_EN)|| \ + (ES_INIT_GPIO_E_12_IRQ_EN)||(ES_INIT_GPIO_F_12_IRQ_EN)||(ES_INIT_GPIO_G_12_IRQ_EN)||(ES_INIT_GPIO_H_12_IRQ_EN) +#define ES_CONF_EXTI_IRQ_12 +#endif + +#if (ES_INIT_GPIO_A_13_IRQ_EN)||(ES_INIT_GPIO_B_13_IRQ_EN)||(ES_INIT_GPIO_C_13_IRQ_EN)||(ES_INIT_GPIO_D_13_IRQ_EN)|| \ + (ES_INIT_GPIO_E_13_IRQ_EN)||(ES_INIT_GPIO_F_13_IRQ_EN)||(ES_INIT_GPIO_G_13_IRQ_EN)||(ES_INIT_GPIO_H_13_IRQ_EN) +#define ES_CONF_EXTI_IRQ_13 +#endif + +#if (ES_INIT_GPIO_A_14_IRQ_EN)||(ES_INIT_GPIO_B_14_IRQ_EN)||(ES_INIT_GPIO_C_14_IRQ_EN)||(ES_INIT_GPIO_D_14_IRQ_EN)|| \ + (ES_INIT_GPIO_E_14_IRQ_EN)||(ES_INIT_GPIO_F_14_IRQ_EN)||(ES_INIT_GPIO_G_14_IRQ_EN)||(ES_INIT_GPIO_H_14_IRQ_EN) +#define ES_CONF_EXTI_IRQ_14 +#endif + +#if (ES_INIT_GPIO_A_15_IRQ_EN)||(ES_INIT_GPIO_B_15_IRQ_EN)||(ES_INIT_GPIO_C_15_IRQ_EN)||(ES_INIT_GPIO_D_15_IRQ_EN)|| \ + (ES_INIT_GPIO_E_15_IRQ_EN)||(ES_INIT_GPIO_F_15_IRQ_EN)||(ES_INIT_GPIO_G_15_IRQ_EN)||(ES_INIT_GPIO_H_15_IRQ_EN) +#define ES_CONF_EXTI_IRQ_15 +#endif + +#endif //11111 + + +/*GPIO外部中断 声明*/ +#if 11111 + +#ifdef ES_CONF_EXTI_IRQ_0 +void irq_pin0_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_1 +void irq_pin1_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_2 +void irq_pin2_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_3 +void irq_pin3_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_4 +void irq_pin4_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_5 +void irq_pin5_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_6 +void irq_pin6_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_7 +void irq_pin7_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_8 +void irq_pin8_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_9 +void irq_pin9_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_10 +void irq_pin10_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_11 +void irq_pin11_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_12 +void irq_pin12_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_13 +void irq_pin13_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_14 +void irq_pin14_callback(void* arg); +#endif + +#ifdef ES_CONF_EXTI_IRQ_15 +void irq_pin15_callback(void* arg); +#endif + + +#endif //11111 + + + + +/*是否有配置的管脚*/ +#if defined(ES_INIT_PIN_GPIO_A_0) || defined(ES_INIT_PIN_GPIO_A_1) || defined(ES_INIT_PIN_GPIO_A_2) || defined(ES_INIT_PIN_GPIO_A_3) || \ + defined(ES_INIT_PIN_GPIO_A_4) || defined(ES_INIT_PIN_GPIO_A_5) || defined(ES_INIT_PIN_GPIO_A_6) || defined(ES_INIT_PIN_GPIO_A_7) || \ + defined(ES_INIT_PIN_GPIO_A_8) || defined(ES_INIT_PIN_GPIO_A_9) || defined(ES_INIT_PIN_GPIO_A_10) || defined(ES_INIT_PIN_GPIO_A_11) || \ + defined(ES_INIT_PIN_GPIO_A_12) || defined(ES_INIT_PIN_GPIO_A_13) || defined(ES_INIT_PIN_GPIO_A_14) || defined(ES_INIT_PIN_GPIO_A_15) || \ + defined(ES_INIT_PIN_GPIO_B_0) || defined(ES_INIT_PIN_GPIO_B_1) || defined(ES_INIT_PIN_GPIO_B_2) || defined(ES_INIT_PIN_GPIO_B_3) || \ + defined(ES_INIT_PIN_GPIO_B_4) || defined(ES_INIT_PIN_GPIO_B_5) || defined(ES_INIT_PIN_GPIO_B_6) || defined(ES_INIT_PIN_GPIO_B_7) || \ + defined(ES_INIT_PIN_GPIO_B_8) || defined(ES_INIT_PIN_GPIO_B_9) || defined(ES_INIT_PIN_GPIO_B_10) || defined(ES_INIT_PIN_GPIO_B_11) || \ + defined(ES_INIT_PIN_GPIO_B_12) || defined(ES_INIT_PIN_GPIO_B_13) || defined(ES_INIT_PIN_GPIO_B_14) || defined(ES_INIT_PIN_GPIO_B_15) || \ + defined(ES_INIT_PIN_GPIO_C_0) || defined(ES_INIT_PIN_GPIO_C_1) || defined(ES_INIT_PIN_GPIO_C_2) || defined(ES_INIT_PIN_GPIO_C_3) || \ + defined(ES_INIT_PIN_GPIO_C_4) || defined(ES_INIT_PIN_GPIO_C_5) || defined(ES_INIT_PIN_GPIO_C_6) || defined(ES_INIT_PIN_GPIO_C_7) || \ + defined(ES_INIT_PIN_GPIO_C_8) || defined(ES_INIT_PIN_GPIO_C_9) || defined(ES_INIT_PIN_GPIO_C_10) || defined(ES_INIT_PIN_GPIO_C_11) || \ + defined(ES_INIT_PIN_GPIO_C_12) || defined(ES_INIT_PIN_GPIO_C_13) || defined(ES_INIT_PIN_GPIO_C_14) || defined(ES_INIT_PIN_GPIO_C_15) || \ + defined(ES_INIT_PIN_GPIO_D_0) || defined(ES_INIT_PIN_GPIO_D_1) || defined(ES_INIT_PIN_GPIO_D_2) || defined(ES_INIT_PIN_GPIO_D_3) || \ + defined(ES_INIT_PIN_GPIO_D_4) || defined(ES_INIT_PIN_GPIO_D_5) || defined(ES_INIT_PIN_GPIO_D_6) || defined(ES_INIT_PIN_GPIO_D_7) || \ + defined(ES_INIT_PIN_GPIO_D_8) || defined(ES_INIT_PIN_GPIO_D_9) || defined(ES_INIT_PIN_GPIO_D_10) || defined(ES_INIT_PIN_GPIO_D_11) || \ + defined(ES_INIT_PIN_GPIO_D_12) || defined(ES_INIT_PIN_GPIO_D_13) || defined(ES_INIT_PIN_GPIO_D_14) || defined(ES_INIT_PIN_GPIO_D_15) || \ + defined(ES_INIT_PIN_GPIO_E_0) || defined(ES_INIT_PIN_GPIO_E_1) || defined(ES_INIT_PIN_GPIO_E_2) || defined(ES_INIT_PIN_GPIO_E_3) || \ + defined(ES_INIT_PIN_GPIO_E_4) || defined(ES_INIT_PIN_GPIO_E_5) || defined(ES_INIT_PIN_GPIO_E_6) || defined(ES_INIT_PIN_GPIO_E_7) || \ + defined(ES_INIT_PIN_GPIO_E_8) || defined(ES_INIT_PIN_GPIO_E_9) || defined(ES_INIT_PIN_GPIO_E_10) || defined(ES_INIT_PIN_GPIO_E_11) || \ + defined(ES_INIT_PIN_GPIO_E_12) || defined(ES_INIT_PIN_GPIO_E_13) || defined(ES_INIT_PIN_GPIO_E_14) || defined(ES_INIT_PIN_GPIO_E_15) || \ + defined(ES_INIT_PIN_GPIO_F_0) || defined(ES_INIT_PIN_GPIO_F_1) || defined(ES_INIT_PIN_GPIO_F_2) || defined(ES_INIT_PIN_GPIO_F_3) || \ + defined(ES_INIT_PIN_GPIO_F_4) || defined(ES_INIT_PIN_GPIO_F_5) || defined(ES_INIT_PIN_GPIO_F_6) || defined(ES_INIT_PIN_GPIO_F_7) || \ + defined(ES_INIT_PIN_GPIO_F_8) || defined(ES_INIT_PIN_GPIO_F_9) || defined(ES_INIT_PIN_GPIO_F_10) || defined(ES_INIT_PIN_GPIO_F_11) || \ + defined(ES_INIT_PIN_GPIO_F_12) || defined(ES_INIT_PIN_GPIO_F_13) || defined(ES_INIT_PIN_GPIO_F_14) || defined(ES_INIT_PIN_GPIO_F_15) || \ + defined(ES_INIT_PIN_GPIO_G_0) || defined(ES_INIT_PIN_GPIO_G_1) || defined(ES_INIT_PIN_GPIO_G_2) || defined(ES_INIT_PIN_GPIO_G_3) || \ + defined(ES_INIT_PIN_GPIO_G_4) || defined(ES_INIT_PIN_GPIO_G_5) || defined(ES_INIT_PIN_GPIO_G_6) || defined(ES_INIT_PIN_GPIO_G_7) || \ + defined(ES_INIT_PIN_GPIO_G_8) || defined(ES_INIT_PIN_GPIO_G_9) || defined(ES_INIT_PIN_GPIO_G_10) || defined(ES_INIT_PIN_GPIO_G_11) || \ + defined(ES_INIT_PIN_GPIO_G_12) || defined(ES_INIT_PIN_GPIO_G_13) || defined(ES_INIT_PIN_GPIO_G_14) || defined(ES_INIT_PIN_GPIO_G_15) || \ + defined(ES_INIT_PIN_GPIO_H_0) || defined(ES_INIT_PIN_GPIO_H_1) || defined(ES_INIT_PIN_GPIO_H_2) || defined(ES_INIT_PIN_GPIO_H_3) || \ + defined(ES_INIT_PIN_GPIO_H_4) || defined(ES_INIT_PIN_GPIO_H_5) || defined(ES_INIT_PIN_GPIO_H_6) || defined(ES_INIT_PIN_GPIO_H_7) || \ + defined(ES_INIT_PIN_GPIO_H_8) || defined(ES_INIT_PIN_GPIO_H_9) || defined(ES_INIT_PIN_GPIO_H_10) || defined(ES_INIT_PIN_GPIO_H_11) || \ + defined(ES_INIT_PIN_GPIO_H_12) || defined(ES_INIT_PIN_GPIO_H_13) || defined(ES_INIT_PIN_GPIO_H_14) || defined(ES_INIT_PIN_GPIO_H_15) + +#define ES_INIT_GPIOS + +#endif + + +#ifdef ES_INIT_GPIOS + +static gpio_conf_t gpio_conf_all[] = +{ + +#ifdef ES_INIT_PIN_GPIO_A_0 + + { + ES_PIN_GPIO_A_0 , + +#ifdef ES_INIT_GPIO_A_0_MODE + ES_INIT_GPIO_A_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_0_LEVEL + ES_INIT_GPIO_A_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_0_IRQ_MODE + ES_INIT_GPIO_A_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_1 + + { + ES_PIN_GPIO_A_1 , + +#ifdef ES_INIT_GPIO_A_1_MODE + ES_INIT_GPIO_A_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_1_LEVEL + ES_INIT_GPIO_A_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_1_IRQ_MODE + ES_INIT_GPIO_A_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_2 + + { + ES_PIN_GPIO_A_2 , + +#ifdef ES_INIT_GPIO_A_2_MODE + ES_INIT_GPIO_A_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_2_LEVEL + ES_INIT_GPIO_A_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_2_IRQ_MODE + ES_INIT_GPIO_A_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_3 + + { + ES_PIN_GPIO_A_3 , + +#ifdef ES_INIT_GPIO_A_3_MODE + ES_INIT_GPIO_A_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_3_LEVEL + ES_INIT_GPIO_A_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_3_IRQ_MODE + ES_INIT_GPIO_A_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_4 + + { + ES_PIN_GPIO_A_4 , + +#ifdef ES_INIT_GPIO_A_4_MODE + ES_INIT_GPIO_A_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_4_LEVEL + ES_INIT_GPIO_A_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_4_IRQ_MODE + ES_INIT_GPIO_A_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_5 + + { + ES_PIN_GPIO_A_5 , + +#ifdef ES_INIT_GPIO_A_5_MODE + ES_INIT_GPIO_A_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_5_LEVEL + ES_INIT_GPIO_A_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_5_IRQ_MODE + ES_INIT_GPIO_A_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_6 + + { + ES_PIN_GPIO_A_6 , + +#ifdef ES_INIT_GPIO_A_6_MODE + ES_INIT_GPIO_A_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_6_LEVEL + ES_INIT_GPIO_A_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_6_IRQ_MODE + ES_INIT_GPIO_A_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_7 + + { + ES_PIN_GPIO_A_7 , + +#ifdef ES_INIT_GPIO_A_7_MODE + ES_INIT_GPIO_A_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_7_LEVEL + ES_INIT_GPIO_A_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_7_IRQ_MODE + ES_INIT_GPIO_A_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_8 + + { + ES_PIN_GPIO_A_8 , + +#ifdef ES_INIT_GPIO_A_8_MODE + ES_INIT_GPIO_A_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_8_LEVEL + ES_INIT_GPIO_A_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_8_IRQ_MODE + ES_INIT_GPIO_A_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_9 + + { + ES_PIN_GPIO_A_9 , + +#ifdef ES_INIT_GPIO_A_9_MODE + ES_INIT_GPIO_A_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_9_LEVEL + ES_INIT_GPIO_A_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_9_IRQ_MODE + ES_INIT_GPIO_A_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_10 + + { + ES_PIN_GPIO_A_10 , + +#ifdef ES_INIT_GPIO_A_10_MODE + ES_INIT_GPIO_A_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_10_LEVEL + ES_INIT_GPIO_A_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_10_IRQ_MODE + ES_INIT_GPIO_A_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_11 + + { + ES_PIN_GPIO_A_11 , + +#ifdef ES_INIT_GPIO_A_11_MODE + ES_INIT_GPIO_A_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_11_LEVEL + ES_INIT_GPIO_A_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_11_IRQ_MODE + ES_INIT_GPIO_A_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_12 + + { + ES_PIN_GPIO_A_12 , + +#ifdef ES_INIT_GPIO_A_12_MODE + ES_INIT_GPIO_A_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_12_LEVEL + ES_INIT_GPIO_A_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_12_IRQ_MODE + ES_INIT_GPIO_A_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_13 + + { + ES_PIN_GPIO_A_13 , + +#ifdef ES_INIT_GPIO_A_13_MODE + ES_INIT_GPIO_A_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_13_LEVEL + ES_INIT_GPIO_A_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_13_IRQ_MODE + ES_INIT_GPIO_A_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_14 + + { + ES_PIN_GPIO_A_14 , + +#ifdef ES_INIT_GPIO_A_14_MODE + ES_INIT_GPIO_A_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_14_LEVEL + ES_INIT_GPIO_A_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_14_IRQ_MODE + ES_INIT_GPIO_A_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_A_15 + + { + ES_PIN_GPIO_A_15 , + +#ifdef ES_INIT_GPIO_A_15_MODE + ES_INIT_GPIO_A_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_A_15_LEVEL + ES_INIT_GPIO_A_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_A_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_A_15_IRQ_MODE + ES_INIT_GPIO_A_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_A_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_0 + + { + ES_PIN_GPIO_B_0 , + +#ifdef ES_INIT_GPIO_B_0_MODE + ES_INIT_GPIO_B_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_0_LEVEL + ES_INIT_GPIO_B_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_0_IRQ_MODE + ES_INIT_GPIO_B_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_1 + + { + ES_PIN_GPIO_B_1 , + +#ifdef ES_INIT_GPIO_B_1_MODE + ES_INIT_GPIO_B_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_1_LEVEL + ES_INIT_GPIO_B_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_1_IRQ_MODE + ES_INIT_GPIO_B_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_2 + + { + ES_PIN_GPIO_B_2 , + +#ifdef ES_INIT_GPIO_B_2_MODE + ES_INIT_GPIO_B_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_2_LEVEL + ES_INIT_GPIO_B_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_2_IRQ_MODE + ES_INIT_GPIO_B_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_3 + + { + ES_PIN_GPIO_B_3 , + +#ifdef ES_INIT_GPIO_B_3_MODE + ES_INIT_GPIO_B_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_3_LEVEL + ES_INIT_GPIO_B_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_3_IRQ_MODE + ES_INIT_GPIO_B_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_4 + + { + ES_PIN_GPIO_B_4 , + +#ifdef ES_INIT_GPIO_B_4_MODE + ES_INIT_GPIO_B_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_4_LEVEL + ES_INIT_GPIO_B_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_4_IRQ_MODE + ES_INIT_GPIO_B_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_5 + + { + ES_PIN_GPIO_B_5 , + +#ifdef ES_INIT_GPIO_B_5_MODE + ES_INIT_GPIO_B_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_5_LEVEL + ES_INIT_GPIO_B_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_5_IRQ_MODE + ES_INIT_GPIO_B_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_6 + + { + ES_PIN_GPIO_B_6 , + +#ifdef ES_INIT_GPIO_B_6_MODE + ES_INIT_GPIO_B_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_6_LEVEL + ES_INIT_GPIO_B_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_6_IRQ_MODE + ES_INIT_GPIO_B_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_7 + + { + ES_PIN_GPIO_B_7 , + +#ifdef ES_INIT_GPIO_B_7_MODE + ES_INIT_GPIO_B_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_7_LEVEL + ES_INIT_GPIO_B_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_7_IRQ_MODE + ES_INIT_GPIO_B_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_8 + + { + ES_PIN_GPIO_B_8 , + +#ifdef ES_INIT_GPIO_B_8_MODE + ES_INIT_GPIO_B_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_8_LEVEL + ES_INIT_GPIO_B_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_8_IRQ_MODE + ES_INIT_GPIO_B_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_9 + + { + ES_PIN_GPIO_B_9 , + +#ifdef ES_INIT_GPIO_B_9_MODE + ES_INIT_GPIO_B_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_9_LEVEL + ES_INIT_GPIO_B_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_9_IRQ_MODE + ES_INIT_GPIO_B_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_10 + + { + ES_PIN_GPIO_B_10 , + +#ifdef ES_INIT_GPIO_B_10_MODE + ES_INIT_GPIO_B_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_10_LEVEL + ES_INIT_GPIO_B_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_10_IRQ_MODE + ES_INIT_GPIO_B_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_11 + + { + ES_PIN_GPIO_B_11 , + +#ifdef ES_INIT_GPIO_B_11_MODE + ES_INIT_GPIO_B_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_11_LEVEL + ES_INIT_GPIO_B_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_11_IRQ_MODE + ES_INIT_GPIO_B_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_12 + + { + ES_PIN_GPIO_B_12 , + +#ifdef ES_INIT_GPIO_B_12_MODE + ES_INIT_GPIO_B_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_12_LEVEL + ES_INIT_GPIO_B_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_12_IRQ_MODE + ES_INIT_GPIO_B_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_13 + + { + ES_PIN_GPIO_B_13 , + +#ifdef ES_INIT_GPIO_B_13_MODE + ES_INIT_GPIO_B_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_13_LEVEL + ES_INIT_GPIO_B_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_13_IRQ_MODE + ES_INIT_GPIO_B_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_14 + + { + ES_PIN_GPIO_B_14 , + +#ifdef ES_INIT_GPIO_B_14_MODE + ES_INIT_GPIO_B_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_14_LEVEL + ES_INIT_GPIO_B_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_14_IRQ_MODE + ES_INIT_GPIO_B_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_B_15 + + { + ES_PIN_GPIO_B_15 , + +#ifdef ES_INIT_GPIO_B_15_MODE + ES_INIT_GPIO_B_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_B_15_LEVEL + ES_INIT_GPIO_B_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_B_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_B_15_IRQ_MODE + ES_INIT_GPIO_B_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_B_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_0 + + { + ES_PIN_GPIO_C_0 , + +#ifdef ES_INIT_GPIO_C_0_MODE + ES_INIT_GPIO_C_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_0_LEVEL + ES_INIT_GPIO_C_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_0_IRQ_MODE + ES_INIT_GPIO_C_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_1 + + { + ES_PIN_GPIO_C_1 , + +#ifdef ES_INIT_GPIO_C_1_MODE + ES_INIT_GPIO_C_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_1_LEVEL + ES_INIT_GPIO_C_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_1_IRQ_MODE + ES_INIT_GPIO_C_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_2 + + { + ES_PIN_GPIO_C_2 , + +#ifdef ES_INIT_GPIO_C_2_MODE + ES_INIT_GPIO_C_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_2_LEVEL + ES_INIT_GPIO_C_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_2_IRQ_MODE + ES_INIT_GPIO_C_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_3 + + { + ES_PIN_GPIO_C_3 , + +#ifdef ES_INIT_GPIO_C_3_MODE + ES_INIT_GPIO_C_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_3_LEVEL + ES_INIT_GPIO_C_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_3_IRQ_MODE + ES_INIT_GPIO_C_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_4 + + { + ES_PIN_GPIO_C_4 , + +#ifdef ES_INIT_GPIO_C_4_MODE + ES_INIT_GPIO_C_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_4_LEVEL + ES_INIT_GPIO_C_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_4_IRQ_MODE + ES_INIT_GPIO_C_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_5 + + { + ES_PIN_GPIO_C_5 , + +#ifdef ES_INIT_GPIO_C_5_MODE + ES_INIT_GPIO_C_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_5_LEVEL + ES_INIT_GPIO_C_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_5_IRQ_MODE + ES_INIT_GPIO_C_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_6 + + { + ES_PIN_GPIO_C_6 , + +#ifdef ES_INIT_GPIO_C_6_MODE + ES_INIT_GPIO_C_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_6_LEVEL + ES_INIT_GPIO_C_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_6_IRQ_MODE + ES_INIT_GPIO_C_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_7 + + { + ES_PIN_GPIO_C_7 , + +#ifdef ES_INIT_GPIO_C_7_MODE + ES_INIT_GPIO_C_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_7_LEVEL + ES_INIT_GPIO_C_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_7_IRQ_MODE + ES_INIT_GPIO_C_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_8 + + { + ES_PIN_GPIO_C_8 , + +#ifdef ES_INIT_GPIO_C_8_MODE + ES_INIT_GPIO_C_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_8_LEVEL + ES_INIT_GPIO_C_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_8_IRQ_MODE + ES_INIT_GPIO_C_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_9 + + { + ES_PIN_GPIO_C_9 , + +#ifdef ES_INIT_GPIO_C_9_MODE + ES_INIT_GPIO_C_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_9_LEVEL + ES_INIT_GPIO_C_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_9_IRQ_MODE + ES_INIT_GPIO_C_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_10 + + { + ES_PIN_GPIO_C_10 , + +#ifdef ES_INIT_GPIO_C_10_MODE + ES_INIT_GPIO_C_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_10_LEVEL + ES_INIT_GPIO_C_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_10_IRQ_MODE + ES_INIT_GPIO_C_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_11 + + { + ES_PIN_GPIO_C_11 , + +#ifdef ES_INIT_GPIO_C_11_MODE + ES_INIT_GPIO_C_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_11_LEVEL + ES_INIT_GPIO_C_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_11_IRQ_MODE + ES_INIT_GPIO_C_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_12 + + { + ES_PIN_GPIO_C_12 , + +#ifdef ES_INIT_GPIO_C_12_MODE + ES_INIT_GPIO_C_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_12_LEVEL + ES_INIT_GPIO_C_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_12_IRQ_MODE + ES_INIT_GPIO_C_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_13 + + { + ES_PIN_GPIO_C_13 , + +#ifdef ES_INIT_GPIO_C_13_MODE + ES_INIT_GPIO_C_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_13_LEVEL + ES_INIT_GPIO_C_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_13_IRQ_MODE + ES_INIT_GPIO_C_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_14 + + { + ES_PIN_GPIO_C_14 , + +#ifdef ES_INIT_GPIO_C_14_MODE + ES_INIT_GPIO_C_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_14_LEVEL + ES_INIT_GPIO_C_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_14_IRQ_MODE + ES_INIT_GPIO_C_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_C_15 + + { + ES_PIN_GPIO_C_15 , + +#ifdef ES_INIT_GPIO_C_15_MODE + ES_INIT_GPIO_C_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_C_15_LEVEL + ES_INIT_GPIO_C_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_C_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_C_15_IRQ_MODE + ES_INIT_GPIO_C_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_C_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_0 + + { + ES_PIN_GPIO_D_0 , + +#ifdef ES_INIT_GPIO_D_0_MODE + ES_INIT_GPIO_D_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_0_LEVEL + ES_INIT_GPIO_D_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_0_IRQ_MODE + ES_INIT_GPIO_D_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_1 + + { + ES_PIN_GPIO_D_1 , + +#ifdef ES_INIT_GPIO_D_1_MODE + ES_INIT_GPIO_D_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_1_LEVEL + ES_INIT_GPIO_D_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_1_IRQ_MODE + ES_INIT_GPIO_D_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_2 + + { + ES_PIN_GPIO_D_2 , + +#ifdef ES_INIT_GPIO_D_2_MODE + ES_INIT_GPIO_D_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_2_LEVEL + ES_INIT_GPIO_D_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_2_IRQ_MODE + ES_INIT_GPIO_D_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_3 + + { + ES_PIN_GPIO_D_3 , + +#ifdef ES_INIT_GPIO_D_3_MODE + ES_INIT_GPIO_D_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_3_LEVEL + ES_INIT_GPIO_D_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_3_IRQ_MODE + ES_INIT_GPIO_D_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_4 + + { + ES_PIN_GPIO_D_4 , + +#ifdef ES_INIT_GPIO_D_4_MODE + ES_INIT_GPIO_D_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_4_LEVEL + ES_INIT_GPIO_D_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_4_IRQ_MODE + ES_INIT_GPIO_D_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_5 + + { + ES_PIN_GPIO_D_5 , + +#ifdef ES_INIT_GPIO_D_5_MODE + ES_INIT_GPIO_D_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_5_LEVEL + ES_INIT_GPIO_D_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_5_IRQ_MODE + ES_INIT_GPIO_D_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_6 + + { + ES_PIN_GPIO_D_6 , + +#ifdef ES_INIT_GPIO_D_6_MODE + ES_INIT_GPIO_D_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_6_LEVEL + ES_INIT_GPIO_D_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_6_IRQ_MODE + ES_INIT_GPIO_D_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_7 + + { + ES_PIN_GPIO_D_7 , + +#ifdef ES_INIT_GPIO_D_7_MODE + ES_INIT_GPIO_D_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_7_LEVEL + ES_INIT_GPIO_D_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_7_IRQ_MODE + ES_INIT_GPIO_D_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_8 + + { + ES_PIN_GPIO_D_8 , + +#ifdef ES_INIT_GPIO_D_8_MODE + ES_INIT_GPIO_D_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_8_LEVEL + ES_INIT_GPIO_D_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_8_IRQ_MODE + ES_INIT_GPIO_D_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_9 + + { + ES_PIN_GPIO_D_9 , + +#ifdef ES_INIT_GPIO_D_9_MODE + ES_INIT_GPIO_D_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_9_LEVEL + ES_INIT_GPIO_D_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_9_IRQ_MODE + ES_INIT_GPIO_D_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_10 + + { + ES_PIN_GPIO_D_10 , + +#ifdef ES_INIT_GPIO_D_10_MODE + ES_INIT_GPIO_D_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_10_LEVEL + ES_INIT_GPIO_D_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_10_IRQ_MODE + ES_INIT_GPIO_D_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_11 + + { + ES_PIN_GPIO_D_11 , + +#ifdef ES_INIT_GPIO_D_11_MODE + ES_INIT_GPIO_D_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_11_LEVEL + ES_INIT_GPIO_D_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_11_IRQ_MODE + ES_INIT_GPIO_D_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_12 + + { + ES_PIN_GPIO_D_12 , + +#ifdef ES_INIT_GPIO_D_12_MODE + ES_INIT_GPIO_D_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_12_LEVEL + ES_INIT_GPIO_D_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_12_IRQ_MODE + ES_INIT_GPIO_D_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_13 + + { + ES_PIN_GPIO_D_13 , + +#ifdef ES_INIT_GPIO_D_13_MODE + ES_INIT_GPIO_D_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_13_LEVEL + ES_INIT_GPIO_D_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_13_IRQ_MODE + ES_INIT_GPIO_D_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_14 + + { + ES_PIN_GPIO_D_14 , + +#ifdef ES_INIT_GPIO_D_14_MODE + ES_INIT_GPIO_D_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_14_LEVEL + ES_INIT_GPIO_D_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_14_IRQ_MODE + ES_INIT_GPIO_D_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_D_15 + + { + ES_PIN_GPIO_D_15 , + +#ifdef ES_INIT_GPIO_D_15_MODE + ES_INIT_GPIO_D_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_D_15_LEVEL + ES_INIT_GPIO_D_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_D_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_D_15_IRQ_MODE + ES_INIT_GPIO_D_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_D_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_0 + + { + ES_PIN_GPIO_E_0 , + +#ifdef ES_INIT_GPIO_E_0_MODE + ES_INIT_GPIO_E_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_0_LEVEL + ES_INIT_GPIO_E_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_0_IRQ_MODE + ES_INIT_GPIO_E_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_1 + + { + ES_PIN_GPIO_E_1 , + +#ifdef ES_INIT_GPIO_E_1_MODE + ES_INIT_GPIO_E_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_1_LEVEL + ES_INIT_GPIO_E_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_1_IRQ_MODE + ES_INIT_GPIO_E_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_2 + + { + ES_PIN_GPIO_E_2 , + +#ifdef ES_INIT_GPIO_E_2_MODE + ES_INIT_GPIO_E_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_2_LEVEL + ES_INIT_GPIO_E_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_2_IRQ_MODE + ES_INIT_GPIO_E_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_3 + + { + ES_PIN_GPIO_E_3 , + +#ifdef ES_INIT_GPIO_E_3_MODE + ES_INIT_GPIO_E_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_3_LEVEL + ES_INIT_GPIO_E_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_3_IRQ_MODE + ES_INIT_GPIO_E_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_4 + + { + ES_PIN_GPIO_E_4 , + +#ifdef ES_INIT_GPIO_E_4_MODE + ES_INIT_GPIO_E_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_4_LEVEL + ES_INIT_GPIO_E_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_4_IRQ_MODE + ES_INIT_GPIO_E_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_5 + + { + ES_PIN_GPIO_E_5 , + +#ifdef ES_INIT_GPIO_E_5_MODE + ES_INIT_GPIO_E_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_5_LEVEL + ES_INIT_GPIO_E_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_5_IRQ_MODE + ES_INIT_GPIO_E_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_6 + + { + ES_PIN_GPIO_E_6 , + +#ifdef ES_INIT_GPIO_E_6_MODE + ES_INIT_GPIO_E_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_6_LEVEL + ES_INIT_GPIO_E_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_6_IRQ_MODE + ES_INIT_GPIO_E_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_7 + + { + ES_PIN_GPIO_E_7 , + +#ifdef ES_INIT_GPIO_E_7_MODE + ES_INIT_GPIO_E_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_7_LEVEL + ES_INIT_GPIO_E_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_7_IRQ_MODE + ES_INIT_GPIO_E_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_8 + + { + ES_PIN_GPIO_E_8 , + +#ifdef ES_INIT_GPIO_E_8_MODE + ES_INIT_GPIO_E_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_8_LEVEL + ES_INIT_GPIO_E_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_8_IRQ_MODE + ES_INIT_GPIO_E_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_9 + + { + ES_PIN_GPIO_E_9 , + +#ifdef ES_INIT_GPIO_E_9_MODE + ES_INIT_GPIO_E_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_9_LEVEL + ES_INIT_GPIO_E_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_9_IRQ_MODE + ES_INIT_GPIO_E_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_10 + + { + ES_PIN_GPIO_E_10 , + +#ifdef ES_INIT_GPIO_E_10_MODE + ES_INIT_GPIO_E_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_10_LEVEL + ES_INIT_GPIO_E_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_10_IRQ_MODE + ES_INIT_GPIO_E_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_11 + + { + ES_PIN_GPIO_E_11 , + +#ifdef ES_INIT_GPIO_E_11_MODE + ES_INIT_GPIO_E_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_11_LEVEL + ES_INIT_GPIO_E_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_11_IRQ_MODE + ES_INIT_GPIO_E_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_12 + + { + ES_PIN_GPIO_E_12 , + +#ifdef ES_INIT_GPIO_E_12_MODE + ES_INIT_GPIO_E_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_12_LEVEL + ES_INIT_GPIO_E_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_12_IRQ_MODE + ES_INIT_GPIO_E_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_13 + + { + ES_PIN_GPIO_E_13 , + +#ifdef ES_INIT_GPIO_E_13_MODE + ES_INIT_GPIO_E_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_13_LEVEL + ES_INIT_GPIO_E_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_13_IRQ_MODE + ES_INIT_GPIO_E_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_14 + + { + ES_PIN_GPIO_E_14 , + +#ifdef ES_INIT_GPIO_E_14_MODE + ES_INIT_GPIO_E_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_14_LEVEL + ES_INIT_GPIO_E_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_14_IRQ_MODE + ES_INIT_GPIO_E_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_E_15 + + { + ES_PIN_GPIO_E_15 , + +#ifdef ES_INIT_GPIO_E_15_MODE + ES_INIT_GPIO_E_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_E_15_LEVEL + ES_INIT_GPIO_E_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_E_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_E_15_IRQ_MODE + ES_INIT_GPIO_E_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_E_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_0 + + { + ES_PIN_GPIO_F_0 , + +#ifdef ES_INIT_GPIO_F_0_MODE + ES_INIT_GPIO_F_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_0_LEVEL + ES_INIT_GPIO_F_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_0_IRQ_MODE + ES_INIT_GPIO_F_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_1 + + { + ES_PIN_GPIO_F_1 , + +#ifdef ES_INIT_GPIO_F_1_MODE + ES_INIT_GPIO_F_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_1_LEVEL + ES_INIT_GPIO_F_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_1_IRQ_MODE + ES_INIT_GPIO_F_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_2 + + { + ES_PIN_GPIO_F_2 , + +#ifdef ES_INIT_GPIO_F_2_MODE + ES_INIT_GPIO_F_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_2_LEVEL + ES_INIT_GPIO_F_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_2_IRQ_MODE + ES_INIT_GPIO_F_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_3 + + { + ES_PIN_GPIO_F_3 , + +#ifdef ES_INIT_GPIO_F_3_MODE + ES_INIT_GPIO_F_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_3_LEVEL + ES_INIT_GPIO_F_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_3_IRQ_MODE + ES_INIT_GPIO_F_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_4 + + { + ES_PIN_GPIO_F_4 , + +#ifdef ES_INIT_GPIO_F_4_MODE + ES_INIT_GPIO_F_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_4_LEVEL + ES_INIT_GPIO_F_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_4_IRQ_MODE + ES_INIT_GPIO_F_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_5 + + { + ES_PIN_GPIO_F_5 , + +#ifdef ES_INIT_GPIO_F_5_MODE + ES_INIT_GPIO_F_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_5_LEVEL + ES_INIT_GPIO_F_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_5_IRQ_MODE + ES_INIT_GPIO_F_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_6 + + { + ES_PIN_GPIO_F_6 , + +#ifdef ES_INIT_GPIO_F_6_MODE + ES_INIT_GPIO_F_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_6_LEVEL + ES_INIT_GPIO_F_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_6_IRQ_MODE + ES_INIT_GPIO_F_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_7 + + { + ES_PIN_GPIO_F_7 , + +#ifdef ES_INIT_GPIO_F_7_MODE + ES_INIT_GPIO_F_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_7_LEVEL + ES_INIT_GPIO_F_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_7_IRQ_MODE + ES_INIT_GPIO_F_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_8 + + { + ES_PIN_GPIO_F_8 , + +#ifdef ES_INIT_GPIO_F_8_MODE + ES_INIT_GPIO_F_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_8_LEVEL + ES_INIT_GPIO_F_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_8_IRQ_MODE + ES_INIT_GPIO_F_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_9 + + { + ES_PIN_GPIO_F_9 , + +#ifdef ES_INIT_GPIO_F_9_MODE + ES_INIT_GPIO_F_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_9_LEVEL + ES_INIT_GPIO_F_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_9_IRQ_MODE + ES_INIT_GPIO_F_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_10 + + { + ES_PIN_GPIO_F_10 , + +#ifdef ES_INIT_GPIO_F_10_MODE + ES_INIT_GPIO_F_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_10_LEVEL + ES_INIT_GPIO_F_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_10_IRQ_MODE + ES_INIT_GPIO_F_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_11 + + { + ES_PIN_GPIO_F_11 , + +#ifdef ES_INIT_GPIO_F_11_MODE + ES_INIT_GPIO_F_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_11_LEVEL + ES_INIT_GPIO_F_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_11_IRQ_MODE + ES_INIT_GPIO_F_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_12 + + { + ES_PIN_GPIO_F_12 , + +#ifdef ES_INIT_GPIO_F_12_MODE + ES_INIT_GPIO_F_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_12_LEVEL + ES_INIT_GPIO_F_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_12_IRQ_MODE + ES_INIT_GPIO_F_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_13 + + { + ES_PIN_GPIO_F_13 , + +#ifdef ES_INIT_GPIO_F_13_MODE + ES_INIT_GPIO_F_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_13_LEVEL + ES_INIT_GPIO_F_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_13_IRQ_MODE + ES_INIT_GPIO_F_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_14 + + { + ES_PIN_GPIO_F_14 , + +#ifdef ES_INIT_GPIO_F_14_MODE + ES_INIT_GPIO_F_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_14_LEVEL + ES_INIT_GPIO_F_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_14_IRQ_MODE + ES_INIT_GPIO_F_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_F_15 + + { + ES_PIN_GPIO_F_15 , + +#ifdef ES_INIT_GPIO_F_15_MODE + ES_INIT_GPIO_F_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_F_15_LEVEL + ES_INIT_GPIO_F_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_F_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_F_15_IRQ_MODE + ES_INIT_GPIO_F_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_F_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_0 + + { + ES_PIN_GPIO_G_0 , + +#ifdef ES_INIT_GPIO_G_0_MODE + ES_INIT_GPIO_G_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_0_LEVEL + ES_INIT_GPIO_G_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_0_IRQ_MODE + ES_INIT_GPIO_G_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_1 + + { + ES_PIN_GPIO_G_1 , + +#ifdef ES_INIT_GPIO_G_1_MODE + ES_INIT_GPIO_G_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_1_LEVEL + ES_INIT_GPIO_G_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_1_IRQ_MODE + ES_INIT_GPIO_G_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_2 + + { + ES_PIN_GPIO_G_2 , + +#ifdef ES_INIT_GPIO_G_2_MODE + ES_INIT_GPIO_G_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_2_LEVEL + ES_INIT_GPIO_G_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_2_IRQ_MODE + ES_INIT_GPIO_G_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_3 + + { + ES_PIN_GPIO_G_3 , + +#ifdef ES_INIT_GPIO_G_3_MODE + ES_INIT_GPIO_G_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_3_LEVEL + ES_INIT_GPIO_G_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_3_IRQ_MODE + ES_INIT_GPIO_G_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_4 + + { + ES_PIN_GPIO_G_4 , + +#ifdef ES_INIT_GPIO_G_4_MODE + ES_INIT_GPIO_G_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_4_LEVEL + ES_INIT_GPIO_G_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_4_IRQ_MODE + ES_INIT_GPIO_G_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_5 + + { + ES_PIN_GPIO_G_5 , + +#ifdef ES_INIT_GPIO_G_5_MODE + ES_INIT_GPIO_G_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_5_LEVEL + ES_INIT_GPIO_G_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_5_IRQ_MODE + ES_INIT_GPIO_G_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_6 + + { + ES_PIN_GPIO_G_6 , + +#ifdef ES_INIT_GPIO_G_6_MODE + ES_INIT_GPIO_G_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_6_LEVEL + ES_INIT_GPIO_G_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_6_IRQ_MODE + ES_INIT_GPIO_G_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_7 + + { + ES_PIN_GPIO_G_7 , + +#ifdef ES_INIT_GPIO_G_7_MODE + ES_INIT_GPIO_G_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_7_LEVEL + ES_INIT_GPIO_G_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_7_IRQ_MODE + ES_INIT_GPIO_G_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_8 + + { + ES_PIN_GPIO_G_8 , + +#ifdef ES_INIT_GPIO_G_8_MODE + ES_INIT_GPIO_G_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_8_LEVEL + ES_INIT_GPIO_G_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_8_IRQ_MODE + ES_INIT_GPIO_G_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_9 + + { + ES_PIN_GPIO_G_9 , + +#ifdef ES_INIT_GPIO_G_9_MODE + ES_INIT_GPIO_G_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_9_LEVEL + ES_INIT_GPIO_G_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_9_IRQ_MODE + ES_INIT_GPIO_G_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_10 + + { + ES_PIN_GPIO_G_10 , + +#ifdef ES_INIT_GPIO_G_10_MODE + ES_INIT_GPIO_G_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_10_LEVEL + ES_INIT_GPIO_G_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_10_IRQ_MODE + ES_INIT_GPIO_G_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_11 + + { + ES_PIN_GPIO_G_11 , + +#ifdef ES_INIT_GPIO_G_11_MODE + ES_INIT_GPIO_G_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_11_LEVEL + ES_INIT_GPIO_G_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_11_IRQ_MODE + ES_INIT_GPIO_G_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_12 + + { + ES_PIN_GPIO_G_12 , + +#ifdef ES_INIT_GPIO_G_12_MODE + ES_INIT_GPIO_G_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_12_LEVEL + ES_INIT_GPIO_G_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_12_IRQ_MODE + ES_INIT_GPIO_G_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_13 + + { + ES_PIN_GPIO_G_13 , + +#ifdef ES_INIT_GPIO_G_13_MODE + ES_INIT_GPIO_G_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_13_LEVEL + ES_INIT_GPIO_G_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_13_IRQ_MODE + ES_INIT_GPIO_G_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_14 + + { + ES_PIN_GPIO_G_14 , + +#ifdef ES_INIT_GPIO_G_14_MODE + ES_INIT_GPIO_G_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_14_LEVEL + ES_INIT_GPIO_G_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_14_IRQ_MODE + ES_INIT_GPIO_G_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_G_15 + + { + ES_PIN_GPIO_G_15 , + +#ifdef ES_INIT_GPIO_G_15_MODE + ES_INIT_GPIO_G_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_G_15_LEVEL + ES_INIT_GPIO_G_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_G_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_G_15_IRQ_MODE + ES_INIT_GPIO_G_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_G_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_0 + + { + ES_PIN_GPIO_H_0 , + +#ifdef ES_INIT_GPIO_H_0_MODE + ES_INIT_GPIO_H_0_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_0_LEVEL + ES_INIT_GPIO_H_0_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_0_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_0_IRQ_MODE + ES_INIT_GPIO_H_0_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin0_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_1 + + { + ES_PIN_GPIO_H_1 , + +#ifdef ES_INIT_GPIO_H_1_MODE + ES_INIT_GPIO_H_1_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_1_LEVEL + ES_INIT_GPIO_H_1_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_1_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_1_IRQ_MODE + ES_INIT_GPIO_H_1_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin1_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_2 + + { + ES_PIN_GPIO_H_2 , + +#ifdef ES_INIT_GPIO_H_2_MODE + ES_INIT_GPIO_H_2_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_2_LEVEL + ES_INIT_GPIO_H_2_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_2_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_2_IRQ_MODE + ES_INIT_GPIO_H_2_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin2_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_3 + + { + ES_PIN_GPIO_H_3 , + +#ifdef ES_INIT_GPIO_H_3_MODE + ES_INIT_GPIO_H_3_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_3_LEVEL + ES_INIT_GPIO_H_3_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_3_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_3_IRQ_MODE + ES_INIT_GPIO_H_3_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin3_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_4 + + { + ES_PIN_GPIO_H_4 , + +#ifdef ES_INIT_GPIO_H_4_MODE + ES_INIT_GPIO_H_4_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_4_LEVEL + ES_INIT_GPIO_H_4_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_4_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_4_IRQ_MODE + ES_INIT_GPIO_H_4_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin4_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_5 + + { + ES_PIN_GPIO_H_5 , + +#ifdef ES_INIT_GPIO_H_5_MODE + ES_INIT_GPIO_H_5_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_5_LEVEL + ES_INIT_GPIO_H_5_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_5_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_5_IRQ_MODE + ES_INIT_GPIO_H_5_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin5_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_6 + + { + ES_PIN_GPIO_H_6 , + +#ifdef ES_INIT_GPIO_H_6_MODE + ES_INIT_GPIO_H_6_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_6_LEVEL + ES_INIT_GPIO_H_6_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_6_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_6_IRQ_MODE + ES_INIT_GPIO_H_6_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin6_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_7 + + { + ES_PIN_GPIO_H_7 , + +#ifdef ES_INIT_GPIO_H_7_MODE + ES_INIT_GPIO_H_7_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_7_LEVEL + ES_INIT_GPIO_H_7_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_7_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_7_IRQ_MODE + ES_INIT_GPIO_H_7_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin7_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_8 + + { + ES_PIN_GPIO_H_8 , + +#ifdef ES_INIT_GPIO_H_8_MODE + ES_INIT_GPIO_H_8_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_8_LEVEL + ES_INIT_GPIO_H_8_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_8_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_8_IRQ_MODE + ES_INIT_GPIO_H_8_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin8_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_9 + + { + ES_PIN_GPIO_H_9 , + +#ifdef ES_INIT_GPIO_H_9_MODE + ES_INIT_GPIO_H_9_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_9_LEVEL + ES_INIT_GPIO_H_9_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_9_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_9_IRQ_MODE + ES_INIT_GPIO_H_9_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin9_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_10 + + { + ES_PIN_GPIO_H_10 , + +#ifdef ES_INIT_GPIO_H_10_MODE + ES_INIT_GPIO_H_10_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_10_LEVEL + ES_INIT_GPIO_H_10_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_10_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_10_IRQ_MODE + ES_INIT_GPIO_H_10_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin10_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_11 + + { + ES_PIN_GPIO_H_11 , + +#ifdef ES_INIT_GPIO_H_11_MODE + ES_INIT_GPIO_H_11_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_11_LEVEL + ES_INIT_GPIO_H_11_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_11_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_11_IRQ_MODE + ES_INIT_GPIO_H_11_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin11_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_12 + + { + ES_PIN_GPIO_H_12 , + +#ifdef ES_INIT_GPIO_H_12_MODE + ES_INIT_GPIO_H_12_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_12_LEVEL + ES_INIT_GPIO_H_12_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_12_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_12_IRQ_MODE + ES_INIT_GPIO_H_12_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin12_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_13 + + { + ES_PIN_GPIO_H_13 , + +#ifdef ES_INIT_GPIO_H_13_MODE + ES_INIT_GPIO_H_13_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_13_LEVEL + ES_INIT_GPIO_H_13_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_13_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_13_IRQ_MODE + ES_INIT_GPIO_H_13_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin13_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_14 + + { + ES_PIN_GPIO_H_14 , + +#ifdef ES_INIT_GPIO_H_14_MODE + ES_INIT_GPIO_H_14_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_14_LEVEL + ES_INIT_GPIO_H_14_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_14_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_14_IRQ_MODE + ES_INIT_GPIO_H_14_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin14_callback , +#else + RT_NULL , +#endif + }, + +#endif + +#ifdef ES_INIT_PIN_GPIO_H_15 + + { + ES_PIN_GPIO_H_15 , + +#ifdef ES_INIT_GPIO_H_15_MODE + ES_INIT_GPIO_H_15_MODE , +#else + ES_C_GPIO_MODE_OUTPUT , +#endif + +#ifdef ES_INIT_GPIO_H_15_LEVEL + ES_INIT_GPIO_H_15_LEVEL , +#else + ES_C_GPIO_LEVEL_HIGH , +#endif + + ES_INIT_GPIO_H_15_IRQ_EN , + +#ifdef ES_INIT_GPIO_H_15_IRQ_MODE + ES_INIT_GPIO_H_15_IRQ_MODE , +#else + ES_C_GPIO_IRQ_MODE_RISE , +#endif + +#if (ES_INIT_GPIO_H_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE) + irq_pin15_callback , +#else + RT_NULL , +#endif + }, + +#endif + + + +}; + +#endif + + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_hwtimer.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_hwtimer.h new file mode 100644 index 0000000000..4dd61b71ec --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_hwtimer.h @@ -0,0 +1,115 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_HWTIMER_H__ +#define __ES_CONF_INFO_HWTIMER_H__ + +#include +#include + +#define ES_C_HWTIMER_MODE_UP HWTIMER_CNTMODE_UP +#define ES_C_HWTIMER_MODE_DOWN HWTIMER_CNTMODE_DW + +/* HWTIMER 配置 */ + +/* codes_main */ + + + +#ifndef ES_AD16C4T0_HWTIMER_MODE +#define ES_AD16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_AD16C4T1_HWTIMER_MODE +#define ES_AD16C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP32C4T0_HWTIMER_MODE +#define ES_GP32C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP32C4T1_HWTIMER_MODE +#define ES_GP32C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP16C4T0_HWTIMER_MODE +#define ES_GP16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_GP16C4T1_HWTIMER_MODE +#define ES_GP16C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T0_HWTIMER_MODE +#define ES_BS16T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif +#ifndef ES_BS16T1_HWTIMER_MODE +#define ES_BS16T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#endif + + + + +#define ES_AD16C4T0_HWTIMER_PRES 1 +#define ES_AD16C4T1_HWTIMER_PRES 1 +#define ES_GP16C4T0_HWTIMER_PRES 1 +#define ES_GP16C4T1_HWTIMER_PRES 1 +#define ES_GP32C4T0_HWTIMER_PRES 1 +#define ES_GP32C4T1_HWTIMER_PRES 1 +#define ES_BS16T0_HWTIMER_PRES 1 +#define ES_BS16T1_HWTIMER_PRES 1 + +#ifndef ES_DEVICE_NAME_AD16C4T0_HWTIMER +#define ES_DEVICE_NAME_AD16C4T0_HWTIMER "timer0" +#endif +#ifndef ES_DEVICE_NAME_AD16C4T1_HWTIMER +#define ES_DEVICE_NAME_AD16C4T1_HWTIMER "timer1" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T0_HWTIMER +#define ES_DEVICE_NAME_GP32C4T0_HWTIMER "timer2" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T1_HWTIMER +#define ES_DEVICE_NAME_GP32C4T1_HWTIMER "timer3" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T0_HWTIMER +#define ES_DEVICE_NAME_GP16C4T0_HWTIMER "timer4" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T1_HWTIMER +#define ES_DEVICE_NAME_GP16C4T1_HWTIMER "timer5" +#endif +#ifndef ES_DEVICE_NAME_BS16T0_HWTIMER +#define ES_DEVICE_NAME_BS16T0_HWTIMER "timer6" +#endif +#ifndef ES_DEVICE_NAME_BS16T1_HWTIMER +#define ES_DEVICE_NAME_BS16T1_HWTIMER "timer7" +#endif + + +#ifdef ss + +#define aa + +#endif + + +#if (1) + +#define BS1 + +#endif + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_i2c.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_i2c.h new file mode 100644 index 0000000000..65310fce01 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_i2c.h @@ -0,0 +1,95 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_I2C_H__ +#define __ES_CONF_INFO_I2C_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + +#define ES_C_I2C_STRETCH I2C_NOSTRETCH_DISABLE +#define ES_C_I2C_NO_STRETCH I2C_NOSTRETCH_ENABLE + +#define ES_C_I2C_GENERALCALL I2C_GENERALCALL_ENABLE +#define ES_C_I2C_NO_GENERALCALL I2C_GENERALCALL_DISABLE + + +#define ES_C_I2C_ADDR_7_MODE I2C_ADDR_7BIT +#define ES_C_I2C_ADDR_10_MODE I2C_ADDR_10BIT + + +/* I2C 配置 */ + + + +/* codes_main */ + + + + + +#ifndef ES_DEVICE_NAME_I2C0 +#define ES_DEVICE_NAME_I2C0 "i2c0" +#endif + +#ifndef ES_DEVICE_NAME_I2C1 +#define ES_DEVICE_NAME_I2C1 "i2c1" +#endif + +#ifndef ES_I2C0_CLK_SPEED +#define ES_I2C0_CLK_SPEED 100000 +#endif +#ifndef ES_I2C0_OWN_ADDR1 +#define ES_I2C0_OWN_ADDR1 0x20 +#endif +#ifndef ES_I2C0_GENERAL_CALL +#define ES_I2C0_GENERAL_CALL ES_C_I2C_NO_GENERALCALL +#endif +#ifndef ES_I2C0_STRETCH +#define ES_I2C0_STRETCH ES_C_I2C_STRETCH +#endif +#ifndef ES_I2C0_ADDR_MODE +#define ES_I2C0_ADDR_MODE ES_C_I2C_ADDR_7_MODE +#endif + +#ifndef ES_I2C1_CLK_SPEED +#define ES_I2C1_CLK_SPEED 100000 +#endif +#ifndef ES_I2C1_OWN_ADDR1 +#define ES_I2C1_OWN_ADDR1 0x20 +#endif +#ifndef ES_I2C1_GENERAL_CALL +#define ES_I2C1_GENERAL_CALL ES_C_I2C_NO_GENERALCALL +#endif +#ifndef ES_I2C1_STRETCH +#define ES_I2C1_STRETCH ES_C_I2C_STRETCH +#endif +#ifndef ES_I2C1_ADDR_MODE +#define ES_I2C1_ADDR_MODE ES_C_I2C_ADDR_7_MODE +#endif + + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_map.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_map.h new file mode 100644 index 0000000000..5ed70f03ff --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_map.h @@ -0,0 +1,1764 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __es_conf_info_map_H__ +#define __es_conf_info_map_H__ + +#include + + + +#define __ES_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index} +#define __ES_PIN_DEFAULT {-1, 0, 0} + +struct pin_index +{ + int index; + GPIO_TypeDef *gpio; + uint32_t pin; +}; + + +#define ES_GPIO_ADC_CH0_GPIO GPIOC +#define ES_GPIO_ADC_CH1_GPIO GPIOC +#define ES_GPIO_ADC_CH2_GPIO GPIOC +#define ES_GPIO_ADC_CH3_GPIO GPIOC +#define ES_GPIO_ADC_CH4_GPIO GPIOA +#define ES_GPIO_ADC_CH5_GPIO GPIOA +#define ES_GPIO_ADC_CH6_GPIO GPIOA +#define ES_GPIO_ADC_CH7_GPIO GPIOA +#define ES_GPIO_ADC_CH8_GPIO GPIOA +#define ES_GPIO_ADC_CH9_GPIO GPIOA +#define ES_GPIO_ADC_CH10_GPIO GPIOA +#define ES_GPIO_ADC_CH11_GPIO GPIOA +#define ES_GPIO_ADC_CH12_GPIO GPIOC +#define ES_GPIO_ADC_CH13_GPIO GPIOC +#define ES_GPIO_ADC_CH14_GPIO GPIOB +#define ES_GPIO_ADC_CH15_GPIO GPIOB + +#define ES_GPIO_ADC_CH0_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH1_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH2_PIN GPIO_PIN_2 +#define ES_GPIO_ADC_CH3_PIN GPIO_PIN_3 +#define ES_GPIO_ADC_CH4_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH5_PIN GPIO_PIN_1 +#define ES_GPIO_ADC_CH6_PIN GPIO_PIN_2 +#define ES_GPIO_ADC_CH7_PIN GPIO_PIN_3 +#define ES_GPIO_ADC_CH8_PIN GPIO_PIN_4 +#define ES_GPIO_ADC_CH9_PIN GPIO_PIN_5 +#define ES_GPIO_ADC_CH10_PIN GPIO_PIN_6 +#define ES_GPIO_ADC_CH11_PIN GPIO_PIN_7 +#define ES_GPIO_ADC_CH12_PIN GPIO_PIN_4 +#define ES_GPIO_ADC_CH13_PIN GPIO_PIN_5 +#define ES_GPIO_ADC_CH14_PIN GPIO_PIN_0 +#define ES_GPIO_ADC_CH15_PIN GPIO_PIN_1 + + + +static const struct pin_index pins[] = +{ + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(2, C, 13), + __ES_PIN(3, C, 14), + __ES_PIN(4, C, 15), + __ES_PIN(5, H, 0), + __ES_PIN(6, H, 1), + __ES_PIN_DEFAULT, + __ES_PIN(8, C, 0), + __ES_PIN(9, C, 1), + __ES_PIN(10, C, 2), + __ES_PIN(11, C, 3), + __ES_PIN(12, H, 3), + __ES_PIN(13, H, 4), + __ES_PIN(14, A, 0), + __ES_PIN(15, A, 1), + __ES_PIN(16, A, 2), + __ES_PIN(17, A, 3), + __ES_PIN(18, F, 0), + __ES_PIN(19, F, 1), + __ES_PIN(20, A, 4), + __ES_PIN(21, A, 5), + __ES_PIN(22, A, 6), + __ES_PIN(23, A, 7), + __ES_PIN(24, C, 4), + __ES_PIN(25, C, 5), + __ES_PIN(26, B, 0), + __ES_PIN(27, B, 1), + __ES_PIN(28, B, 2), + __ES_PIN(29, B, 10), + __ES_PIN(30, B, 11), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(33, B, 12), + __ES_PIN(34, B, 13), + __ES_PIN(35, B, 14), + __ES_PIN(36, B, 15), + __ES_PIN(37, C, 6), + __ES_PIN(38, C, 7), + __ES_PIN(39, C, 8), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(46, A, 13), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, + __ES_PIN(49, A, 14), + __ES_PIN(50, A, 15), + __ES_PIN(51, C, 10), + __ES_PIN(52, C, 11), + __ES_PIN(53, C, 12), + __ES_PIN(54, D, 2), + __ES_PIN(55, B, 3), + __ES_PIN(56, B, 4), + __ES_PIN(57, B, 5), + __ES_PIN(58, B, 6), + __ES_PIN(59, B, 7), + __ES_PIN(60, H, 2), + __ES_PIN(61, B, 8), + __ES_PIN(62, B, 9), + __ES_PIN_DEFAULT, + __ES_PIN_DEFAULT, +}; + +#define ES_PIN_GPIO_C_13 2 +#define ES_PIN_GPIO_C_14 3 +#define ES_PIN_GPIO_C_15 4 +#define ES_PIN_GPIO_H_0 5 +#define ES_PIN_GPIO_H_1 6 +#define ES_PIN_GPIO_C_0 8 +#define ES_PIN_GPIO_C_1 9 +#define ES_PIN_GPIO_C_2 10 +#define ES_PIN_GPIO_C_3 11 +#define ES_PIN_GPIO_H_3 12 +#define ES_PIN_GPIO_H_4 13 +#define ES_PIN_GPIO_A_0 14 +#define ES_PIN_GPIO_A_1 15 +#define ES_PIN_GPIO_A_2 16 +#define ES_PIN_GPIO_A_3 17 +#define ES_PIN_GPIO_F_0 18 +#define ES_PIN_GPIO_F_1 19 +#define ES_PIN_GPIO_A_4 20 +#define ES_PIN_GPIO_A_5 21 +#define ES_PIN_GPIO_A_6 22 +#define ES_PIN_GPIO_A_7 23 +#define ES_PIN_GPIO_C_4 24 +#define ES_PIN_GPIO_C_5 25 +#define ES_PIN_GPIO_B_0 26 +#define ES_PIN_GPIO_B_1 27 +#define ES_PIN_GPIO_B_2 28 +#define ES_PIN_GPIO_B_10 29 +#define ES_PIN_GPIO_B_11 30 +#define ES_PIN_GPIO_B_12 33 +#define ES_PIN_GPIO_B_13 34 +#define ES_PIN_GPIO_B_14 35 +#define ES_PIN_GPIO_B_15 36 +#define ES_PIN_GPIO_C_6 37 +#define ES_PIN_GPIO_C_7 38 +#define ES_PIN_GPIO_C_8 39 +#define ES_PIN_GPIO_A_13 46 +#define ES_PIN_GPIO_A_14 49 +#define ES_PIN_GPIO_A_15 50 +#define ES_PIN_GPIO_C_10 51 +#define ES_PIN_GPIO_C_11 52 +#define ES_PIN_GPIO_C_12 53 +#define ES_PIN_GPIO_D_2 54 +#define ES_PIN_GPIO_B_3 55 +#define ES_PIN_GPIO_B_4 56 +#define ES_PIN_GPIO_B_5 57 +#define ES_PIN_GPIO_B_6 58 +#define ES_PIN_GPIO_B_7 59 +#define ES_PIN_GPIO_H_2 60 +#define ES_PIN_GPIO_B_8 61 +#define ES_PIN_GPIO_B_9 62 + + + +/* UART_TX */ + + +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_10 +#endif +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOH +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_0 +#endif +#ifndef ES_UART0_TX_GPIO_FUNC +#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_TX_GPIO_PORT +#define ES_UART0_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_TX_GPIO_PIN +#define ES_UART0_TX_GPIO_PIN GPIO_PIN_8 +#endif +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_0 +#endif +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_13 +#endif +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_10 +#endif +#ifndef ES_UART1_TX_GPIO_FUNC +#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_TX_GPIO_PORT +#define ES_UART1_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_TX_GPIO_PIN +#define ES_UART1_TX_GPIO_PIN GPIO_PIN_5 +#endif +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_2 +#endif +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_12 +#endif +#ifndef ES_UART2_TX_GPIO_FUNC +#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_TX_GPIO_PORT +#define ES_UART2_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART2_TX_GPIO_PIN +#define ES_UART2_TX_GPIO_PIN GPIO_PIN_3 +#endif +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_4 +#endif +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_10 +#endif +#ifndef ES_UART3_TX_GPIO_FUNC +#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_TX_GPIO_PORT +#define ES_UART3_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART3_TX_GPIO_PIN +#define ES_UART3_TX_GPIO_PIN GPIO_PIN_14 +#endif +#ifndef ES_UART4_TX_GPIO_FUNC +#define ES_UART4_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_TX_GPIO_PORT +#define ES_UART4_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART4_TX_GPIO_PIN +#define ES_UART4_TX_GPIO_PIN GPIO_PIN_6 +#endif +#ifndef ES_UART4_TX_GPIO_FUNC +#define ES_UART4_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_TX_GPIO_PORT +#define ES_UART4_TX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_TX_GPIO_PIN +#define ES_UART4_TX_GPIO_PIN GPIO_PIN_10 +#endif +#ifndef ES_UART5_TX_GPIO_FUNC +#define ES_UART5_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_TX_GPIO_PORT +#define ES_UART5_TX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_TX_GPIO_PIN +#define ES_UART5_TX_GPIO_PIN GPIO_PIN_2 +#endif +#ifndef ES_UART5_TX_GPIO_FUNC +#define ES_UART5_TX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART5_TX_GPIO_PORT +#define ES_UART5_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART5_TX_GPIO_PIN +#define ES_UART5_TX_GPIO_PIN GPIO_PIN_9 +#endif +#ifndef ES_UART5_TX_GPIO_FUNC +#define ES_UART5_TX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_TX_GPIO_PORT +#define ES_UART5_TX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_TX_GPIO_PIN +#define ES_UART5_TX_GPIO_PIN GPIO_PIN_5 +#endif + +/* UART_RX */ + + +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_11 +#endif +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOH +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_1 +#endif +#ifndef ES_UART0_RX_GPIO_FUNC +#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RX_GPIO_PORT +#define ES_UART0_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_RX_GPIO_PIN +#define ES_UART0_RX_GPIO_PIN GPIO_PIN_9 +#endif +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_1 +#endif +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_14 +#endif +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_11 +#endif +#ifndef ES_UART1_RX_GPIO_FUNC +#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RX_GPIO_PORT +#define ES_UART1_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_RX_GPIO_PIN +#define ES_UART1_RX_GPIO_PIN GPIO_PIN_6 +#endif +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_4 +#endif +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_3 +#endif +#ifndef ES_UART2_RX_GPIO_FUNC +#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RX_GPIO_PORT +#define ES_UART2_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART2_RX_GPIO_PIN +#define ES_UART2_RX_GPIO_PIN GPIO_PIN_2 +#endif +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOC +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_5 +#endif +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_11 +#endif +#ifndef ES_UART3_RX_GPIO_FUNC +#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RX_GPIO_PORT +#define ES_UART3_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART3_RX_GPIO_PIN +#define ES_UART3_RX_GPIO_PIN GPIO_PIN_13 +#endif +#ifndef ES_UART4_RX_GPIO_FUNC +#define ES_UART4_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_RX_GPIO_PORT +#define ES_UART4_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART4_RX_GPIO_PIN +#define ES_UART4_RX_GPIO_PIN GPIO_PIN_7 +#endif +#ifndef ES_UART4_RX_GPIO_FUNC +#define ES_UART4_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_RX_GPIO_PORT +#define ES_UART4_RX_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_RX_GPIO_PIN +#define ES_UART4_RX_GPIO_PIN GPIO_PIN_11 +#endif +#ifndef ES_UART5_RX_GPIO_FUNC +#define ES_UART5_RX_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART5_RX_GPIO_PORT +#define ES_UART5_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_UART5_RX_GPIO_PIN +#define ES_UART5_RX_GPIO_PIN GPIO_PIN_8 +#endif +#ifndef ES_UART5_RX_GPIO_FUNC +#define ES_UART5_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_RX_GPIO_PORT +#define ES_UART5_RX_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_RX_GPIO_PIN +#define ES_UART5_RX_GPIO_PIN GPIO_PIN_3 +#endif +#ifndef ES_UART5_RX_GPIO_FUNC +#define ES_UART5_RX_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_RX_GPIO_PORT +#define ES_UART5_RX_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_RX_GPIO_PIN +#define ES_UART5_RX_GPIO_PIN GPIO_PIN_6 +#endif + +/* UART_RTS */ + + +#ifndef ES_UART0_RTS_GPIO_FUNC +#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_RTS_GPIO_PORT +#define ES_UART0_RTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_RTS_GPIO_PIN +#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_14 +#endif +#ifndef ES_UART0_RTS_GPIO_FUNC +#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_RTS_GPIO_PORT +#define ES_UART0_RTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_RTS_GPIO_PIN +#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_12 +#endif +#ifndef ES_UART1_RTS_GPIO_FUNC +#define ES_UART1_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RTS_GPIO_PORT +#define ES_UART1_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RTS_GPIO_PIN +#define ES_UART1_RTS_GPIO_PIN GPIO_PIN_3 +#endif +#ifndef ES_UART1_RTS_GPIO_FUNC +#define ES_UART1_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_RTS_GPIO_PORT +#define ES_UART1_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_RTS_GPIO_PIN +#define ES_UART1_RTS_GPIO_PIN GPIO_PIN_12 +#endif +#ifndef ES_UART2_RTS_GPIO_FUNC +#define ES_UART2_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_RTS_GPIO_PORT +#define ES_UART2_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_RTS_GPIO_PIN +#define ES_UART2_RTS_GPIO_PIN GPIO_PIN_5 +#endif +#ifndef ES_UART2_RTS_GPIO_FUNC +#define ES_UART2_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_RTS_GPIO_PORT +#define ES_UART2_RTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_RTS_GPIO_PIN +#define ES_UART2_RTS_GPIO_PIN GPIO_PIN_10 +#endif +#ifndef ES_UART3_RTS_GPIO_FUNC +#define ES_UART3_RTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_RTS_GPIO_PORT +#define ES_UART3_RTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART3_RTS_GPIO_PIN +#define ES_UART3_RTS_GPIO_PIN GPIO_PIN_1 +#endif +#ifndef ES_UART3_RTS_GPIO_FUNC +#define ES_UART3_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_RTS_GPIO_PORT +#define ES_UART3_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_RTS_GPIO_PIN +#define ES_UART3_RTS_GPIO_PIN GPIO_PIN_13 +#endif +#ifndef ES_UART4_RTS_GPIO_FUNC +#define ES_UART4_RTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_RTS_GPIO_PORT +#define ES_UART4_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_RTS_GPIO_PIN +#define ES_UART4_RTS_GPIO_PIN GPIO_PIN_13 +#endif +#ifndef ES_UART4_RTS_GPIO_FUNC +#define ES_UART4_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_RTS_GPIO_PORT +#define ES_UART4_RTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_RTS_GPIO_PIN +#define ES_UART4_RTS_GPIO_PIN GPIO_PIN_1 +#endif +#ifndef ES_UART5_RTS_GPIO_FUNC +#define ES_UART5_RTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_RTS_GPIO_PORT +#define ES_UART5_RTS_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_RTS_GPIO_PIN +#define ES_UART5_RTS_GPIO_PIN GPIO_PIN_1 +#endif +#ifndef ES_UART5_RTS_GPIO_FUNC +#define ES_UART5_RTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_RTS_GPIO_PORT +#define ES_UART5_RTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_RTS_GPIO_PIN +#define ES_UART5_RTS_GPIO_PIN GPIO_PIN_4 +#endif + +/* UART_CTS */ + + +#ifndef ES_UART0_CTS_GPIO_FUNC +#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART0_CTS_GPIO_PORT +#define ES_UART0_CTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART0_CTS_GPIO_PIN +#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_13 +#endif +#ifndef ES_UART0_CTS_GPIO_FUNC +#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART0_CTS_GPIO_PORT +#define ES_UART0_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART0_CTS_GPIO_PIN +#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_11 +#endif +#ifndef ES_UART1_CTS_GPIO_FUNC +#define ES_UART1_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_CTS_GPIO_PORT +#define ES_UART1_CTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART1_CTS_GPIO_PIN +#define ES_UART1_CTS_GPIO_PIN GPIO_PIN_2 +#endif +#ifndef ES_UART1_CTS_GPIO_FUNC +#define ES_UART1_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART1_CTS_GPIO_PORT +#define ES_UART1_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART1_CTS_GPIO_PIN +#define ES_UART1_CTS_GPIO_PIN GPIO_PIN_2 +#endif +#ifndef ES_UART2_CTS_GPIO_FUNC +#define ES_UART2_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART2_CTS_GPIO_PORT +#define ES_UART2_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART2_CTS_GPIO_PIN +#define ES_UART2_CTS_GPIO_PIN GPIO_PIN_4 +#endif +#ifndef ES_UART2_CTS_GPIO_FUNC +#define ES_UART2_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART2_CTS_GPIO_PORT +#define ES_UART2_CTS_GPIO_PORT GPIOC +#endif +#ifndef ES_UART2_CTS_GPIO_PIN +#define ES_UART2_CTS_GPIO_PIN GPIO_PIN_11 +#endif +#ifndef ES_UART3_CTS_GPIO_FUNC +#define ES_UART3_CTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART3_CTS_GPIO_PORT +#define ES_UART3_CTS_GPIO_PORT GPIOB +#endif +#ifndef ES_UART3_CTS_GPIO_PIN +#define ES_UART3_CTS_GPIO_PIN GPIO_PIN_0 +#endif +#ifndef ES_UART3_CTS_GPIO_FUNC +#define ES_UART3_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART3_CTS_GPIO_PORT +#define ES_UART3_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART3_CTS_GPIO_PIN +#define ES_UART3_CTS_GPIO_PIN GPIO_PIN_12 +#endif +#ifndef ES_UART4_CTS_GPIO_FUNC +#define ES_UART4_CTS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_CTS_GPIO_PORT +#define ES_UART4_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CTS_GPIO_PIN +#define ES_UART4_CTS_GPIO_PIN GPIO_PIN_12 +#endif +#ifndef ES_UART4_CTS_GPIO_FUNC +#define ES_UART4_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_CTS_GPIO_PORT +#define ES_UART4_CTS_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CTS_GPIO_PIN +#define ES_UART4_CTS_GPIO_PIN GPIO_PIN_0 +#endif +#ifndef ES_UART5_CTS_GPIO_FUNC +#define ES_UART5_CTS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_CTS_GPIO_PORT +#define ES_UART5_CTS_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_CTS_GPIO_PIN +#define ES_UART5_CTS_GPIO_PIN GPIO_PIN_0 +#endif +#ifndef ES_UART5_CTS_GPIO_FUNC +#define ES_UART5_CTS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_CTS_GPIO_PORT +#define ES_UART5_CTS_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_CTS_GPIO_PIN +#define ES_UART5_CTS_GPIO_PIN GPIO_PIN_3 +#endif + +/* UART_CK */ + + +#ifndef ES_UART4_CK_GPIO_FUNC +#define ES_UART4_CK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART4_CK_GPIO_PORT +#define ES_UART4_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CK_GPIO_PIN +#define ES_UART4_CK_GPIO_PIN GPIO_PIN_6 +#endif +#ifndef ES_UART4_CK_GPIO_FUNC +#define ES_UART4_CK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART4_CK_GPIO_PORT +#define ES_UART4_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_UART4_CK_GPIO_PIN +#define ES_UART4_CK_GPIO_PIN GPIO_PIN_7 +#endif +#ifndef ES_UART5_CK_GPIO_FUNC +#define ES_UART5_CK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_UART5_CK_GPIO_PORT +#define ES_UART5_CK_GPIO_PORT GPIOA +#endif +#ifndef ES_UART5_CK_GPIO_PIN +#define ES_UART5_CK_GPIO_PIN GPIO_PIN_4 +#endif +#ifndef ES_UART5_CK_GPIO_FUNC +#define ES_UART5_CK_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_UART5_CK_GPIO_PORT +#define ES_UART5_CK_GPIO_PORT GPIOD +#endif +#ifndef ES_UART5_CK_GPIO_PIN +#define ES_UART5_CK_GPIO_PIN GPIO_PIN_7 +#endif +#ifndef ES_UART5_CK_GPIO_FUNC +#define ES_UART5_CK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_UART5_CK_GPIO_PORT +#define ES_UART5_CK_GPIO_PORT GPIOE +#endif +#ifndef ES_UART5_CK_GPIO_PIN +#define ES_UART5_CK_GPIO_PIN GPIO_PIN_0 +#endif + +/* USART_TX */ + + + +/* USART_RX */ + + + +/* USART_RTS */ + + + +/* USART_CTS */ + + + +/* USART_CK */ + + + +/* I2C_SCL */ + + +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN GPIO_PIN_6 +#endif +#ifndef ES_I2C0_SCL_GPIO_FUNC +#define ES_I2C0_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SCL_GPIO_PORT +#define ES_I2C0_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SCL_GPIO_PIN +#define ES_I2C0_SCL_GPIO_PIN GPIO_PIN_8 +#endif +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_10 +#endif +#ifndef ES_I2C1_SCL_GPIO_FUNC +#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SCL_GPIO_PORT +#define ES_I2C1_SCL_GPIO_PORT GPIOH +#endif +#ifndef ES_I2C1_SCL_GPIO_PIN +#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_0 +#endif + +/* I2C_SDA */ + + +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN GPIO_PIN_7 +#endif +#ifndef ES_I2C0_SDA_GPIO_FUNC +#define ES_I2C0_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C0_SDA_GPIO_PORT +#define ES_I2C0_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C0_SDA_GPIO_PIN +#define ES_I2C0_SDA_GPIO_PIN GPIO_PIN_9 +#endif +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOA +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_6 +#endif +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOB +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_11 +#endif +#ifndef ES_I2C1_SDA_GPIO_FUNC +#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_I2C1_SDA_GPIO_PORT +#define ES_I2C1_SDA_GPIO_PORT GPIOH +#endif +#ifndef ES_I2C1_SDA_GPIO_PIN +#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_1 +#endif + +/* SPI_MISO */ + + +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_4 +#endif +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_6 +#endif +#ifndef ES_SPI0_MISO_GPIO_FUNC +#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MISO_GPIO_PORT +#define ES_SPI0_MISO_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_MISO_GPIO_PIN +#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_4 +#endif +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN GPIO_PIN_2 +#endif +#ifndef ES_SPI1_MISO_GPIO_FUNC +#define ES_SPI1_MISO_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MISO_GPIO_PORT +#define ES_SPI1_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_MISO_GPIO_PIN +#define ES_SPI1_MISO_GPIO_PIN GPIO_PIN_14 +#endif +#ifndef ES_SPI2_MISO_GPIO_FUNC +#define ES_SPI2_MISO_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_MISO_GPIO_PORT +#define ES_SPI2_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MISO_GPIO_PIN +#define ES_SPI2_MISO_GPIO_PIN GPIO_PIN_4 +#endif +#ifndef ES_SPI2_MISO_GPIO_FUNC +#define ES_SPI2_MISO_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_MISO_GPIO_PORT +#define ES_SPI2_MISO_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MISO_GPIO_PIN +#define ES_SPI2_MISO_GPIO_PIN GPIO_PIN_0 +#endif + +/* SPI_MOSI */ + + +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_5 +#endif +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_7 +#endif +#ifndef ES_SPI0_MOSI_GPIO_FUNC +#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_MOSI_GPIO_PORT +#define ES_SPI0_MOSI_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_MOSI_GPIO_PIN +#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_7 +#endif +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN GPIO_PIN_3 +#endif +#ifndef ES_SPI1_MOSI_GPIO_FUNC +#define ES_SPI1_MOSI_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_MOSI_GPIO_PORT +#define ES_SPI1_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_MOSI_GPIO_PIN +#define ES_SPI1_MOSI_GPIO_PIN GPIO_PIN_15 +#endif +#ifndef ES_SPI2_MOSI_GPIO_FUNC +#define ES_SPI2_MOSI_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_MOSI_GPIO_PORT +#define ES_SPI2_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MOSI_GPIO_PIN +#define ES_SPI2_MOSI_GPIO_PIN GPIO_PIN_5 +#endif +#ifndef ES_SPI2_MOSI_GPIO_FUNC +#define ES_SPI2_MOSI_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_MOSI_GPIO_PORT +#define ES_SPI2_MOSI_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_MOSI_GPIO_PIN +#define ES_SPI2_MOSI_GPIO_PIN GPIO_PIN_1 +#endif + +/* SPI_SCK */ + + +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_3 +#endif +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_5 +#endif +#ifndef ES_SPI0_SCK_GPIO_FUNC +#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_SCK_GPIO_PORT +#define ES_SPI0_SCK_GPIO_PORT GPIOD +#endif +#ifndef ES_SPI0_SCK_GPIO_PIN +#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_3 +#endif +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN GPIO_PIN_1 +#endif +#ifndef ES_SPI1_SCK_GPIO_FUNC +#define ES_SPI1_SCK_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_SCK_GPIO_PORT +#define ES_SPI1_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_SCK_GPIO_PIN +#define ES_SPI1_SCK_GPIO_PIN GPIO_PIN_13 +#endif +#ifndef ES_SPI2_SCK_GPIO_FUNC +#define ES_SPI2_SCK_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_SCK_GPIO_PORT +#define ES_SPI2_SCK_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI2_SCK_GPIO_PIN +#define ES_SPI2_SCK_GPIO_PIN GPIO_PIN_5 +#endif +#ifndef ES_SPI2_SCK_GPIO_FUNC +#define ES_SPI2_SCK_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_SCK_GPIO_PORT +#define ES_SPI2_SCK_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI2_SCK_GPIO_PIN +#define ES_SPI2_SCK_GPIO_PIN GPIO_PIN_3 +#endif + +/* SPI_NSS */ + + +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN GPIO_PIN_4 +#endif +#ifndef ES_SPI0_NSS_GPIO_FUNC +#define ES_SPI0_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI0_NSS_GPIO_PORT +#define ES_SPI0_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI0_NSS_GPIO_PIN +#define ES_SPI0_NSS_GPIO_PIN GPIO_PIN_15 +#endif +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN GPIO_PIN_0 +#endif +#ifndef ES_SPI1_NSS_GPIO_FUNC +#define ES_SPI1_NSS_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_SPI1_NSS_GPIO_PORT +#define ES_SPI1_NSS_GPIO_PORT GPIOB +#endif +#ifndef ES_SPI1_NSS_GPIO_PIN +#define ES_SPI1_NSS_GPIO_PIN GPIO_PIN_12 +#endif +#ifndef ES_SPI2_NSS_GPIO_FUNC +#define ES_SPI2_NSS_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_SPI2_NSS_GPIO_PORT +#define ES_SPI2_NSS_GPIO_PORT GPIOC +#endif +#ifndef ES_SPI2_NSS_GPIO_PIN +#define ES_SPI2_NSS_GPIO_PIN GPIO_PIN_4 +#endif +#ifndef ES_SPI2_NSS_GPIO_FUNC +#define ES_SPI2_NSS_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_SPI2_NSS_GPIO_PORT +#define ES_SPI2_NSS_GPIO_PORT GPIOA +#endif +#ifndef ES_SPI2_NSS_GPIO_PIN +#define ES_SPI2_NSS_GPIO_PIN GPIO_PIN_15 +#endif + +/* CAN_TX */ + + +#ifndef ES_CAN0_TX_GPIO_FUNC +#define ES_CAN0_TX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_CAN0_TX_GPIO_PORT +#define ES_CAN0_TX_GPIO_PORT GPIOB +#endif +#ifndef ES_CAN0_TX_GPIO_PIN +#define ES_CAN0_TX_GPIO_PIN GPIO_PIN_9 +#endif + +/* CAN_RX */ + + +#ifndef ES_CAN0_RX_GPIO_FUNC +#define ES_CAN0_RX_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_CAN0_RX_GPIO_PORT +#define ES_CAN0_RX_GPIO_PORT GPIOB +#endif +#ifndef ES_CAN0_RX_GPIO_PIN +#define ES_CAN0_RX_GPIO_PIN GPIO_PIN_8 +#endif + +/* AD16C4T_CH1 */ + + +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN GPIO_PIN_7 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_FUNC +#define ES_AD16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PORT +#define ES_AD16C4T0_CH1_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH1_GPIO_PIN +#define ES_AD16C4T0_CH1_GPIO_PIN GPIO_PIN_9 +#endif +#ifndef ES_AD16C4T1_CH1_GPIO_FUNC +#define ES_AD16C4T1_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH1_GPIO_PORT +#define ES_AD16C4T1_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T1_CH1_GPIO_PIN +#define ES_AD16C4T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif + +/* AD16C4T_CH2 */ + + +#ifndef ES_AD16C4T0_CH2_GPIO_FUNC +#define ES_AD16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PORT +#define ES_AD16C4T0_CH2_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH2_GPIO_PIN +#define ES_AD16C4T0_CH2_GPIO_PIN GPIO_PIN_11 +#endif +#ifndef ES_AD16C4T1_CH2_GPIO_FUNC +#define ES_AD16C4T1_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH2_GPIO_PORT +#define ES_AD16C4T1_CH2_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T1_CH2_GPIO_PIN +#define ES_AD16C4T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +/* AD16C4T_CH3 */ + + +#ifndef ES_AD16C4T0_CH3_GPIO_FUNC +#define ES_AD16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PORT +#define ES_AD16C4T0_CH3_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH3_GPIO_PIN +#define ES_AD16C4T0_CH3_GPIO_PIN GPIO_PIN_13 +#endif +#ifndef ES_AD16C4T1_CH3_GPIO_FUNC +#define ES_AD16C4T1_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH3_GPIO_PORT +#define ES_AD16C4T1_CH3_GPIO_PORT GPIOC +#endif +#ifndef ES_AD16C4T1_CH3_GPIO_PIN +#define ES_AD16C4T1_CH3_GPIO_PIN GPIO_PIN_8 +#endif + +/* AD16C4T_CH4 */ + + +#ifndef ES_AD16C4T0_CH4_GPIO_FUNC +#define ES_AD16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PORT +#define ES_AD16C4T0_CH4_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH4_GPIO_PIN +#define ES_AD16C4T0_CH4_GPIO_PIN GPIO_PIN_14 +#endif + +/* AD16C4T_CH1N */ + + +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_13 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC +#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PORT +#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH1N_GPIO_PIN +#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_8 +#endif +#ifndef ES_AD16C4T1_CH1N_GPIO_FUNC +#define ES_AD16C4T1_CH1N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T1_CH1N_GPIO_PORT +#define ES_AD16C4T1_CH1N_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T1_CH1N_GPIO_PIN +#define ES_AD16C4T1_CH1N_GPIO_PIN GPIO_PIN_7 +#endif + +/* AD16C4T_CH2N */ + + +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_14 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC +#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PORT +#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH2N_GPIO_PIN +#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_10 +#endif +#ifndef ES_AD16C4T1_CH2N_GPIO_FUNC +#define ES_AD16C4T1_CH2N_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T1_CH2N_GPIO_PORT +#define ES_AD16C4T1_CH2N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T1_CH2N_GPIO_PIN +#define ES_AD16C4T1_CH2N_GPIO_PIN GPIO_PIN_0 +#endif + +/* AD16C4T_CH3N */ + + +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_15 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC +#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PORT +#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_CH3N_GPIO_PIN +#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_12 +#endif +#ifndef ES_AD16C4T1_CH3N_GPIO_FUNC +#define ES_AD16C4T1_CH3N_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_AD16C4T1_CH3N_GPIO_PORT +#define ES_AD16C4T1_CH3N_GPIO_PORT GPIOB +#endif +#ifndef ES_AD16C4T1_CH3N_GPIO_PIN +#define ES_AD16C4T1_CH3N_GPIO_PIN GPIO_PIN_1 +#endif + +/* AD16C4T_CH4N */ + + + +/* AD16C4T_ET */ + + +#ifndef ES_AD16C4T0_ET_GPIO_FUNC +#define ES_AD16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PORT +#define ES_AD16C4T0_ET_GPIO_PORT GPIOE +#endif +#ifndef ES_AD16C4T0_ET_GPIO_PIN +#define ES_AD16C4T0_ET_GPIO_PIN GPIO_PIN_7 +#endif +#ifndef ES_AD16C4T1_ET_GPIO_FUNC +#define ES_AD16C4T1_ET_GPIO_FUNC GPIO_FUNC_4 +#endif +#ifndef ES_AD16C4T1_ET_GPIO_PORT +#define ES_AD16C4T1_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_AD16C4T1_ET_GPIO_PIN +#define ES_AD16C4T1_ET_GPIO_PIN GPIO_PIN_0 +#endif + +/* GP32C4T_CH1 */ + + +#ifndef ES_GP32C4T0_CH1_GPIO_FUNC +#define ES_GP32C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PORT +#define ES_GP32C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PIN +#define ES_GP32C4T0_CH1_GPIO_PIN GPIO_PIN_0 +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_FUNC +#define ES_GP32C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PORT +#define ES_GP32C4T0_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH1_GPIO_PIN +#define ES_GP32C4T0_CH1_GPIO_PIN GPIO_PIN_15 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_FUNC +#define ES_GP32C4T1_CH1_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PORT +#define ES_GP32C4T1_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PIN +#define ES_GP32C4T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_FUNC +#define ES_GP32C4T1_CH1_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PORT +#define ES_GP32C4T1_CH1_GPIO_PORT GPIOC +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PIN +#define ES_GP32C4T1_CH1_GPIO_PIN GPIO_PIN_6 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_FUNC +#define ES_GP32C4T1_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PORT +#define ES_GP32C4T1_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH1_GPIO_PIN +#define ES_GP32C4T1_CH1_GPIO_PIN GPIO_PIN_4 +#endif + +/* GP32C4T_CH2 */ + + +#ifndef ES_GP32C4T0_CH2_GPIO_FUNC +#define ES_GP32C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PORT +#define ES_GP32C4T0_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PIN +#define ES_GP32C4T0_CH2_GPIO_PIN GPIO_PIN_1 +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_FUNC +#define ES_GP32C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PORT +#define ES_GP32C4T0_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T0_CH2_GPIO_PIN +#define ES_GP32C4T0_CH2_GPIO_PIN GPIO_PIN_3 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_FUNC +#define ES_GP32C4T1_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PORT +#define ES_GP32C4T1_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PIN +#define ES_GP32C4T1_CH2_GPIO_PIN GPIO_PIN_5 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_FUNC +#define ES_GP32C4T1_CH2_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PORT +#define ES_GP32C4T1_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PIN +#define ES_GP32C4T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_FUNC +#define ES_GP32C4T1_CH2_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PORT +#define ES_GP32C4T1_CH2_GPIO_PORT GPIOC +#endif +#ifndef ES_GP32C4T1_CH2_GPIO_PIN +#define ES_GP32C4T1_CH2_GPIO_PIN GPIO_PIN_7 +#endif + +/* GP32C4T_CH3 */ + + +#ifndef ES_GP32C4T0_CH3_GPIO_FUNC +#define ES_GP32C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PORT +#define ES_GP32C4T0_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PIN +#define ES_GP32C4T0_CH3_GPIO_PIN GPIO_PIN_2 +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_FUNC +#define ES_GP32C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PORT +#define ES_GP32C4T0_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T0_CH3_GPIO_PIN +#define ES_GP32C4T0_CH3_GPIO_PIN GPIO_PIN_10 +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_FUNC +#define ES_GP32C4T1_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PORT +#define ES_GP32C4T1_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PIN +#define ES_GP32C4T1_CH3_GPIO_PIN GPIO_PIN_0 +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_FUNC +#define ES_GP32C4T1_CH3_GPIO_FUNC GPIO_FUNC_3 +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PORT +#define ES_GP32C4T1_CH3_GPIO_PORT GPIOC +#endif +#ifndef ES_GP32C4T1_CH3_GPIO_PIN +#define ES_GP32C4T1_CH3_GPIO_PIN GPIO_PIN_8 +#endif + +/* GP32C4T_CH4 */ + + +#ifndef ES_GP32C4T0_CH4_GPIO_FUNC +#define ES_GP32C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PORT +#define ES_GP32C4T0_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PIN +#define ES_GP32C4T0_CH4_GPIO_PIN GPIO_PIN_11 +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_FUNC +#define ES_GP32C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PORT +#define ES_GP32C4T0_CH4_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_CH4_GPIO_PIN +#define ES_GP32C4T0_CH4_GPIO_PIN GPIO_PIN_3 +#endif +#ifndef ES_GP32C4T1_CH4_GPIO_FUNC +#define ES_GP32C4T1_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_CH4_GPIO_PORT +#define ES_GP32C4T1_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP32C4T1_CH4_GPIO_PIN +#define ES_GP32C4T1_CH4_GPIO_PIN GPIO_PIN_1 +#endif + +/* GP32C4T_ET */ + + +#ifndef ES_GP32C4T0_ET_GPIO_FUNC +#define ES_GP32C4T0_ET_GPIO_FUNC GPIO_FUNC_6 +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PORT +#define ES_GP32C4T0_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PIN +#define ES_GP32C4T0_ET_GPIO_PIN GPIO_PIN_0 +#endif +#ifndef ES_GP32C4T0_ET_GPIO_FUNC +#define ES_GP32C4T0_ET_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PORT +#define ES_GP32C4T0_ET_GPIO_PORT GPIOA +#endif +#ifndef ES_GP32C4T0_ET_GPIO_PIN +#define ES_GP32C4T0_ET_GPIO_PIN GPIO_PIN_15 +#endif +#ifndef ES_GP32C4T1_ET_GPIO_FUNC +#define ES_GP32C4T1_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP32C4T1_ET_GPIO_PORT +#define ES_GP32C4T1_ET_GPIO_PORT GPIOD +#endif +#ifndef ES_GP32C4T1_ET_GPIO_PIN +#define ES_GP32C4T1_ET_GPIO_PIN GPIO_PIN_2 +#endif + +/* GP16C4T_CH1 */ + + +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN GPIO_PIN_6 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_FUNC +#define ES_GP16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PORT +#define ES_GP16C4T0_CH1_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH1_GPIO_PIN +#define ES_GP16C4T0_CH1_GPIO_PIN GPIO_PIN_12 +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_FUNC +#define ES_GP16C4T1_CH1_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_PORT +#define ES_GP16C4T1_CH1_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH1_GPIO_PIN +#define ES_GP16C4T1_CH1_GPIO_PIN GPIO_PIN_0 +#endif + +/* GP16C4T_CH2 */ + + +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN GPIO_PIN_7 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_FUNC +#define ES_GP16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PORT +#define ES_GP16C4T0_CH2_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH2_GPIO_PIN +#define ES_GP16C4T0_CH2_GPIO_PIN GPIO_PIN_13 +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_FUNC +#define ES_GP16C4T1_CH2_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_PORT +#define ES_GP16C4T1_CH2_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH2_GPIO_PIN +#define ES_GP16C4T1_CH2_GPIO_PIN GPIO_PIN_1 +#endif + +/* GP16C4T_CH3 */ + + +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN GPIO_PIN_8 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_FUNC +#define ES_GP16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PORT +#define ES_GP16C4T0_CH3_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH3_GPIO_PIN +#define ES_GP16C4T0_CH3_GPIO_PIN GPIO_PIN_14 +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_FUNC +#define ES_GP16C4T1_CH3_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_PORT +#define ES_GP16C4T1_CH3_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH3_GPIO_PIN +#define ES_GP16C4T1_CH3_GPIO_PIN GPIO_PIN_2 +#endif + +/* GP16C4T_CH4 */ + + +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOB +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN GPIO_PIN_9 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_FUNC +#define ES_GP16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PORT +#define ES_GP16C4T0_CH4_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T0_CH4_GPIO_PIN +#define ES_GP16C4T0_CH4_GPIO_PIN GPIO_PIN_15 +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_FUNC +#define ES_GP16C4T1_CH4_GPIO_FUNC GPIO_FUNC_5 +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_PORT +#define ES_GP16C4T1_CH4_GPIO_PORT GPIOA +#endif +#ifndef ES_GP16C4T1_CH4_GPIO_PIN +#define ES_GP16C4T1_CH4_GPIO_PIN GPIO_PIN_3 +#endif + +/* GP16C4T_ET */ + + +#ifndef ES_GP16C4T0_ET_GPIO_FUNC +#define ES_GP16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PORT +#define ES_GP16C4T0_ET_GPIO_PORT GPIOE +#endif +#ifndef ES_GP16C4T0_ET_GPIO_PIN +#define ES_GP16C4T0_ET_GPIO_PIN GPIO_PIN_0 +#endif +#ifndef ES_GP16C4T1_ET_GPIO_FUNC +#define ES_GP16C4T1_ET_GPIO_FUNC GPIO_FUNC_2 +#endif +#ifndef ES_GP16C4T1_ET_GPIO_PORT +#define ES_GP16C4T1_ET_GPIO_PORT GPIOD +#endif +#ifndef ES_GP16C4T1_ET_GPIO_PIN +#define ES_GP16C4T1_ET_GPIO_PIN GPIO_PIN_3 +#endif + + + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pm.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pm.h new file mode 100644 index 0000000000..580268312c --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pm.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_PM_H__ +#define __ES_CONF_INFO_PM_H__ + +#include +#include + +#define ES_PMU_SAVE_LOAD_UART + +/* PM 配置 */ + + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pwm.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pwm.h new file mode 100644 index 0000000000..86010a80ce --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_pwm.h @@ -0,0 +1,78 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_PWM_H__ +#define __ES_CONF_INFO_PWM_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + + +#define ES_C_PWM_OC_POL_HIGH TIMER_OC_POLARITY_HIGH +#define ES_C_PWM_OC_POL_LOW TIMER_OC_POLARITY_LOW + +#define ES_C_PWM_OC_MODE_PWM1 TIMER_OC_MODE_PWM1 +#define ES_C_PWM_OC_MODE_PWM2 TIMER_OC_MODE_PWM2 + + + +/* PWM 配置 */ + + +/* codes_main */ + + + +#define ES_PWM_OC_POLARITY ES_C_PWM_OC_POL_HIGH +#define ES_PWM_OC_MODE ES_C_PWM_OC_MODE_PWM2 + +#ifndef ES_PWM_OC_POLARITY +#define ES_PWM_OC_POLARITY ES_C_PWM_OC_POL_HIGH +#endif +#ifndef ES_PWM_OC_MODE +#define ES_PWM_OC_MODE ES_C_PWM_OC_MODE_PWM2 +#endif + +#ifndef ES_DEVICE_NAME_AD16C4T0_PWM +#define ES_DEVICE_NAME_AD16C4T0_PWM "pwm0" +#endif +#ifndef ES_DEVICE_NAME_AD16C4T1_PWM +#define ES_DEVICE_NAME_AD16C4T1_PWM "pwm1" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T0_PWM +#define ES_DEVICE_NAME_GP32C4T0_PWM "pwm2" +#endif +#ifndef ES_DEVICE_NAME_GP32C4T1_PWM +#define ES_DEVICE_NAME_GP32C4T1_PWM "pwm3" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T0_PWM +#define ES_DEVICE_NAME_GP16C4T0_PWM "pwm4" +#endif +#ifndef ES_DEVICE_NAME_GP16C4T1_PWM +#define ES_DEVICE_NAME_GP16C4T1_PWM "pwm5" +#endif + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_rtc.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_rtc.h new file mode 100644 index 0000000000..2aa8faf9d7 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_rtc.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_RTC_H__ +#define __ES_CONF_INFO_RTC_H__ + +#include +#include + +/* RTC 配置 */ + +#define ES_C_RTC_SOURCE_LRC RTC_SOURCE_LRC +#define ES_C_RTC_SOURCE_LOSC RTC_SOURCE_LOSC + +#define ES_RTC_CLK_SOURCE ES_C_RTC_SOURCE_LOSC + + + + +/* codes_main */ + + +#ifndef ES_DEVICE_NAME_RTC +#define ES_DEVICE_NAME_RTC "rtc" +#endif + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_select.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_select.h new file mode 100644 index 0000000000..06a28d6fd0 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_select.h @@ -0,0 +1,43 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_SELECT_H__ +#define __ES_CONF_INFO_SELECT_H__ + + +#define ES_C_ENABLE 1 +#define ES_C_DISABLE 0 + + +/* codes_main */ + +#ifndef ES_USE_ASSERT +#define ES_USE_ASSERT ES_C_DISABLE +#endif + + +#if ES_USE_ASSERT + #define USE_ASSERT +#endif + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_spi.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_spi.h new file mode 100644 index 0000000000..c9cf895aeb --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_spi.h @@ -0,0 +1,159 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_SPI_H__ +#define __ES_CONF_INFO_SPI_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + +/* SPI 配置 */ + +#define SPI_BUS_CONFIG(_CONF_,_I_) do{_CONF_.mode = 0U; \ + _CONF_.mode |= ( ES_SPI##_I_##_MASTER_SLAVE | \ + ES_SPI##_I_##_WIRE_3_4 | \ + ES_SPI##_I_##_CPHA_1_2 | \ + ES_SPI##_I_##_CPOL_H_L | \ + ES_SPI##_I_##_CS | \ + ES_SPI##_I_##_M_L_SB ); \ + _CONF_.data_width = ES_SPI##_I_##_DATA_W; \ + _CONF_.max_hz = ES_SPI##_I_##_MAX_HZ; \ + }while(0) + + +// spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ +// spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ +// spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ +// spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ +// spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ +// spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ +// spi_config.data_width = 8; /* 数据长度：8 */ +// spi_config.max_hz = 2000000; /* 最快时钟频率 */ + +#define ES_C_SPI_CLK_POL_HIGH RT_SPI_CPOL +#define ES_C_SPI_CLK_POL_LOW !RT_SPI_CPOL + +#define ES_C_SPI_CLK_PHA_FIRST !RT_SPI_CPHA +#define ES_C_SPI_CLK_PHA_SECOND RT_SPI_CPHA + +#define ES_C_SPI_MSB RT_SPI_MSB +#define ES_C_SPI_LSB RT_SPI_LSB + +#define ES_C_SPI_CS_LOW_LEVEL 0 +#define ES_C_SPI_CS_HIGH_LEVEL 1 + +/* codes_main */ + + +#ifndef ES_DEVICE_NAME_SPI0_BUS +#define ES_DEVICE_NAME_SPI0_BUS "spi0" +#endif +#ifndef ES_DEVICE_NAME_SPI0_DEV0 +#define ES_DEVICE_NAME_SPI0_DEV0 "spi00" +#endif + +#ifndef ES_DEVICE_NAME_SPI1_BUS +#define ES_DEVICE_NAME_SPI1_BUS "spi1" +#endif +#ifndef ES_DEVICE_NAME_SPI1_DEV0 +#define ES_DEVICE_NAME_SPI1_DEV0 "spi10" +#endif + +#ifndef ES_DEVICE_NAME_SPI2_BUS +#define ES_DEVICE_NAME_SPI2_BUS "spi2" +#endif +#ifndef ES_DEVICE_NAME_SPI2_DEV0 +#define ES_DEVICE_NAME_SPI2_DEV0 "spi20" +#endif + + +#define ES_SPI_CS_LEVEL ES_C_SPI_CS_LOW_LEVEL + +#ifndef ES_SPI0_CPHA_1_2 +#define ES_SPI0_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI0_CPOL_H_L +#define ES_SPI0_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI0_M_L_SB +#define ES_SPI0_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI0_MAX_HZ +#define ES_SPI0_MAX_HZ 2000000 +#endif +#ifndef ES_SPI0_NSS_PIN +#define ES_SPI0_NSS_PIN 0xFFFFFFFF +#endif + +#ifndef ES_SPI1_CPHA_1_2 +#define ES_SPI1_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI1_CPOL_H_L +#define ES_SPI1_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI1_M_L_SB +#define ES_SPI1_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI1_MAX_HZ +#define ES_SPI1_MAX_HZ 2000000 +#endif +#ifndef ES_SPI1_NSS_PIN +#define ES_SPI1_NSS_PIN 0xFFFFFFFF +#endif + +#ifndef ES_SPI2_CPHA_1_2 +#define ES_SPI2_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND +#endif +#ifndef ES_SPI2_CPOL_H_L +#define ES_SPI2_CPOL_H_L ES_C_SPI_CLK_POL_HIGH +#endif +#ifndef ES_SPI2_M_L_SB +#define ES_SPI2_M_L_SB RT_SPI_MSB +#endif +#ifndef ES_SPI2_MAX_HZ +#define ES_SPI2_MAX_HZ 2000000 +#endif +#ifndef ES_SPI2_NSS_PIN +#define ES_SPI2_NSS_PIN 0xFFFFFFFF +#endif + + +#define ES_SPI0_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI0_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI0_CS RT_SPI_NO_CS +#define ES_SPI0_DATA_W 8 + +#define ES_SPI1_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI1_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI1_CS RT_SPI_NO_CS +#define ES_SPI1_DATA_W 8 + +#define ES_SPI2_MASTER_SLAVE !RT_SPI_SLAVE +#define ES_SPI2_WIRE_3_4 !RT_SPI_3WIRE +#define ES_SPI2_CS RT_SPI_NO_CS +#define ES_SPI2_DATA_W 8 + + +#endif diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_uart.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_uart.h new file mode 100644 index 0000000000..430cb9f599 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_uart.h @@ -0,0 +1,205 @@ +/* + * Change Logs: + * Date Author Notes + * 2021-04-20 liuhy the first version + * + * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef __ES_CONF_INFO_UART_H__ +#define __ES_CONF_INFO_UART_H__ + +#include "es_conf_info_map.h" +#include +#include +#include + + + +#define ES_C_UART_PARITY_NONE PARITY_NONE +#define ES_C_UART_PARITY_ODD PARITY_ODD +#define ES_C_UART_PARITY_EVEN PARITY_EVEN + +#define ES_C_UART_STOP_1 STOP_BITS_1 +#define ES_C_UART_STOP_2 STOP_BITS_2 + + +/* UART 配置 */ + +/* codes_main */ + + + +#ifndef ES_DEVICE_NAME_UART0 +#define ES_DEVICE_NAME_UART0 "uart0" +#endif +#ifndef ES_DEVICE_NAME_UART1 +#define ES_DEVICE_NAME_UART1 "uart1" +#endif +#ifndef ES_DEVICE_NAME_UART2 +#define ES_DEVICE_NAME_UART2 "uart2" +#endif +#ifndef ES_DEVICE_NAME_UART3 +#define ES_DEVICE_NAME_UART3 "uart3" +#endif +#ifndef ES_DEVICE_NAME_UART4 +#define ES_DEVICE_NAME_UART4 "uart4" +#endif +#ifndef ES_DEVICE_NAME_UART5 +#define ES_DEVICE_NAME_UART5 "uart5" +#endif + +#ifndef ES_CONF_UART0_BAUD_RATE +#define ES_CONF_UART0_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART0_PARITY +#define ES_CONF_UART0_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART0_STOP_BITS +#define ES_CONF_UART0_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART1_BAUD_RATE +#define ES_CONF_UART1_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART1_PARITY +#define ES_CONF_UART1_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART1_STOP_BITS +#define ES_CONF_UART1_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART2_BAUD_RATE +#define ES_CONF_UART2_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART2_PARITY +#define ES_CONF_UART2_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART2_STOP_BITS +#define ES_CONF_UART2_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART3_BAUD_RATE +#define ES_CONF_UART3_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART3_PARITY +#define ES_CONF_UART3_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART3_STOP_BITS +#define ES_CONF_UART3_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART4_BAUD_RATE +#define ES_CONF_UART4_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART4_PARITY +#define ES_CONF_UART4_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART4_STOP_BITS +#define ES_CONF_UART4_STOP_BITS ES_C_UART_STOP_1 +#endif + +#ifndef ES_CONF_UART5_BAUD_RATE +#define ES_CONF_UART5_BAUD_RATE 115200 +#endif +#ifndef ES_CONF_UART5_PARITY +#define ES_CONF_UART5_PARITY ES_C_UART_PARITY_NONE +#endif +#ifndef ES_CONF_UART5_STOP_BITS +#define ES_CONF_UART5_STOP_BITS ES_C_UART_STOP_1 +#endif + + +#define ES_UART0_CONFIG \ +{ \ + ES_CONF_UART0_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART0_STOP_BITS, \ + ES_CONF_UART0_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART1_CONFIG \ +{ \ + ES_CONF_UART1_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART1_STOP_BITS, \ + ES_CONF_UART1_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART2_CONFIG \ +{ \ + ES_CONF_UART2_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART2_STOP_BITS, \ + ES_CONF_UART2_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART3_CONFIG \ +{ \ + ES_CONF_UART3_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART3_STOP_BITS, \ + ES_CONF_UART3_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART4_CONFIG \ +{ \ + ES_CONF_UART4_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART4_STOP_BITS, \ + ES_CONF_UART4_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + + +#define ES_UART5_CONFIG \ +{ \ + ES_CONF_UART5_BAUD_RATE, \ + DATA_BITS_8, \ + ES_CONF_UART5_STOP_BITS, \ + ES_CONF_UART5_PARITY, \ + BIT_ORDER_LSB, \ + NRZ_NORMAL, \ + RT_SERIAL_RB_BUFSZ, \ + 0 \ +} + +#endif diff --git a/bsp/essemi/es32f369x/drivers/Kconfig b/bsp/essemi/es32f369x/drivers/Kconfig index 4b42e7e074..b6c10b5376 100644 --- a/bsp/essemi/es32f369x/drivers/Kconfig +++ b/bsp/essemi/es32f369x/drivers/Kconfig @@ -1,134 +1,14 @@ menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" config BSP_USING_GPIO bool "Enable GPIO" select RT_USING_PIN default y - menu "UART Drivers" - config BSP_USING_UART0 - bool "Enable UART0 PB10/PB11(T/R)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART1 - bool "Enable UART1 PC10/PC11(T/R)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART2 - bool "Enable UART2 PC12/PD02(T/R)" - select RT_USING_SERIAL - default y - - config BSP_USING_UART3 - bool "Enable UART3 PC04/PC05(T/R)" - select RT_USING_SERIAL - default n - depends on !BSP_USING_SPI2 - - config BSP_USING_UART4 - bool "Enable UART4 PB06/PB07(T/R)" - select RT_USING_SERIAL - default n - depends on !BSP_USING_I2C0 - depends on !BSP_USING_PWM0 - - config BSP_USING_UART5 - bool "Enable UART5 PB09/PB08(T/R)" - select RT_USING_SERIAL - default n - depends on !BSP_USING_PWM0 - endmenu - - menu "SPI Drivers" - config BSP_USING_SPI0 - bool "Enable SPI0 BUS PB03/PB04/PB05(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - - config BSP_USING_SPI1 - bool "Enable SPI1 BUS PC01/PC02/PC03(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - - config BSP_USING_SPI2 - bool "Enable SPI2 BUS PC05/PB00/PB01(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - depends on !BSP_USING_UART3 - endmenu - - menu "I2C Drivers" - config BSP_USING_I2C0 - bool "Enable I2C0 BUS PB06/PB07(SCL/SDA)" - select RT_USING_I2C - default n - depends on !BSP_USING_PWM0 - - config BSP_USING_I2C1 - bool "Enable I2C1 BUS PA05/PA06(SCL/SDA)" - select RT_USING_I2C - default n - endmenu - - menu "CAN Drivers" - config BSP_USING_CAN - bool "Enable CAN BUS PB08/PB09(RX/TX)" - select RT_USING_CAN - default n - endmenu - - menu "ADC Drivers" - config BSP_USING_ADC - bool "Using ADC" - select RT_USING_ADC - default n - endmenu - - menu "RTC Drivers" - config BSP_USING_RTC - bool "Using RTC" - select RT_USING_RTC - default n - endmenu - - menu "HWtimer Drivers" - config BSP_USING_HWTIMER0 - bool "Using timer0" - select RT_USING_HWTIMER - default n - - config BSP_USING_HWTIMER1 - bool "Using timer1" - select RT_USING_HWTIMER - default n - endmenu - - menu "PWM Drivers" - config BSP_USING_PWM0 - bool "Using PWM0 PB06/PB07/PB08/PB09" - select RT_USING_PWM - default n - depends on !BSP_USING_CAN - depends on !BSP_USING_I2C0 - - config BSP_USING_PWM1 - bool "Using PWM1 PA00/PA01/PA02/PA03" - select RT_USING_PWM - default n - endmenu - - menu "PM Drivers" - config BSP_USING_PM - bool "Using PM" - select RT_USING_PM - default n - endmenu + source "drivers/ES/Kconfig" endmenu @@ -157,11 +37,11 @@ menu "Hardware Drivers Config" config BSP_USING_EXAMPLE_LED_BLINK bool "BSP_USING_EXAMPLE_LED_BLINK" - default y + default n config BSP_USING_EXAMPLE_PIN_BEEP bool "BSP_USING_EXAMPLE_PIN_BEEP" - default y + default n config BSP_USING_EXAMPLE_PWM_LED bool "BSP_USING_EXAMPLE_PWM_LED" @@ -177,7 +57,7 @@ menu "Hardware Drivers Config" config BSP_USING_EXAMPLE_UART bool "BSP_USING_EXAMPLE_UART" - default y + default n config BSP_USING_EXAMPLE_CAN bool "BSP_USING_EXAMPLE_CAN" diff --git a/bsp/essemi/es32f369x/drivers/SConscript b/bsp/essemi/es32f369x/drivers/SConscript index 735ebb37be..e0c0053e66 100644 --- a/bsp/essemi/es32f369x/drivers/SConscript +++ b/bsp/essemi/es32f369x/drivers/SConscript @@ -15,7 +15,9 @@ if GetDepend('RT_USING_PIN'): # add serial driver code if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3') or \ - GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5'): + GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5') or \ + GetDepend('BSP_USING_USART0') or GetDepend('BSP_USING_USART1') or GetDepend('BSP_USING_USART2') or GetDepend('BSP_USING_USART3') or \ + GetDepend('BSP_USING_USART4') or GetDepend('BSP_USING_USART5'): src += ['drv_uart.c'] # add spi driver code @@ -27,11 +29,11 @@ if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'): src += ['drv_i2c.c'] # add can driver code -if GetDepend('BSP_USING_CAN'): +if GetDepend('BSP_USING_CAN') or GetDepend('BSP_USING_CAN0') or GetDepend('RT_USING_CAN'): src += ['drv_can.c'] # add adc driver code -if GetDepend(['BSP_USING_ADC']): +if GetDepend(['BSP_USING_ADC0']) or GetDepend('BSP_USING_ADC1'): src += ['drv_adc.c'] # add rtc driver code @@ -39,11 +41,16 @@ if GetDepend(['BSP_USING_RTC']): src += ['drv_rtc.c'] # add hwtimer driver code -if GetDepend('BSP_USING_HWTIMER0') or GetDepend('BSP_USING_HWTIMER1'): +if GetDepend('BSP_USING_AD16C4T0_HWTIMER') or GetDepend('BSP_USING_AD16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP32C4T0_HWTIMER') or GetDepend('BSP_USING_GP32C4T1_HWTIMER') or \ + GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \ + GetDepend('BSP_USING_BS16T0_HWTIMER') or GetDepend('BSP_USING_BS16T1_HWTIMER'): src += ['drv_hwtimer.c'] # add pwm driver code -if GetDepend('BSP_USING_PWM0') or GetDepend('BSP_USING_PWM1'): +if GetDepend('BSP_USING_AD16C4T0_PWM') or GetDepend('BSP_USING_AD16C4T1_PWM') or \ + GetDepend('BSP_USING_GP32C4T0_PWM') or GetDepend('BSP_USING_GP32C4T1_PWM') or \ + GetDepend('BSP_USING_GP16C4T0_PWM') or GetDepend('BSP_USING_GP16C4T1_PWM'): src += ['drv_pwm.c'] # add pm driver code @@ -56,7 +63,7 @@ objs = objs + group src = [] cwd = GetCurrentDir() -include_path = [cwd] +include_path = [cwd + '/ES'] if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'): src += ['bsp_driver_example/adc_vol_sample.c'] diff --git a/bsp/essemi/es32f369x/drivers/board.c b/bsp/essemi/es32f369x/drivers/board.c index 1c2b834177..ea42df63dc 100644 --- a/bsp/essemi/es32f369x/drivers/board.c +++ b/bsp/essemi/es32f369x/drivers/board.c @@ -1,11 +1,24 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include @@ -13,7 +26,6 @@ #include "board.h" #include "drv_uart.h" #include "drv_gpio.h" -#include #include /** @@ -42,11 +54,68 @@ void NVIC_Configuration(void) *******************************************************************************/ void SystemClock_Config(void) { - /* hosc 12MHz, from hosc/3 pll to 96MHz */ - ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_96M); - /* SYSCLK 96MHz */ - ald_cmu_clock_config(CMU_CLOCK_PLL1, 96000000); + + SYSCFG_UNLOCK(); +#if ES_CMU_LRC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); +#endif /*ES_CMU_LRC_EN*/ + +#if ES_CMU_LOSC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); +#endif /*ES_CMU_LOSC_EN*/ + +#if ES_CMU_HRC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); +#endif /*ES_CMU_HRC_EN*/ + +#if ES_CMU_HOSC_EN + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); +#endif /*ES_CMU_HOSC_EN*/ + + SYSCFG_LOCK(); + +#if ES_CMU_PLL1_EN + /*PLL的源必须是4M*/ + ald_cmu_pll1_config(ES_PLL1_REFER_CLK, ES_PLL1_OUT_CLK); + + #if ES_CMU_PLL1_SAFE_EN + ald_cmu_pll_safe_config(ENABLE); + #else + ald_cmu_pll_safe_config(DISABLE); + #endif + +#else + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); +#endif /*ES_CMU_PLL1_EN*/ + + ald_cmu_clock_config(ES_SYS_CLK_SOURSE, ES_SYS_CLK); + + ald_cmu_div_config(CMU_SYS,ES_CMU_SYS_DIV); + ald_cmu_div_config(CMU_HCLK_1,ES_CMU_HCLK_1_DIV); + ald_cmu_div_config(CMU_HCLK_2,ES_CMU_HCLK_2_DIV); + ald_cmu_div_config(CMU_PCLK_1,ES_CMU_PCLK_1_DIV); + ald_cmu_div_config(CMU_PCLK_2,ES_CMU_PCLK_2_DIV); + ald_cmu_perh_clock_config(CMU_PERH_ALL, ENABLE); + +/*低功耗时钟使能*/ +#ifdef RT_USING_PM + SYSCFG_UNLOCK(); + SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); + SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); + SYSCFG_LOCK(); +#endif + } /******************************************************************************* @@ -70,11 +139,21 @@ void SysTick_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); + ald_inc_tick(); rt_tick_increase(); /* leave interrupt */ rt_interrupt_leave(); } +/** + * This is the cmu interrupt service. + * + */ +void CMU_Handler(void) +{ + ald_cmu_irq_handler(); +} + /*@}*/ /** * This function will initial ES32F3 board. diff --git a/bsp/essemi/es32f369x/drivers/board.h b/bsp/essemi/es32f369x/drivers/board.h index 628c2f87fd..640cf44864 100644 --- a/bsp/essemi/es32f369x/drivers/board.h +++ b/bsp/essemi/es32f369x/drivers/board.h @@ -1,11 +1,24 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ // <<< Use Configuration Wizard in Context Menu >>> @@ -13,6 +26,7 @@ #define __BOARD_H__ #include +#include "es_conf_info_cmu.h" #define ES32F3_SRAM_SIZE 0x18000 #define ES32F3_SRAM_END (0x20000000 + ES32F3_SRAM_SIZE) diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c index f9444982d4..9576736bcd 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/adc_vol_sample.c @@ -18,11 +18,15 @@ #include #include + +#ifdef RT_USING_ADC + #define ADC_DEV_NAME "adc0" /* ADC 设备名称 */ #define ADC_DEV_CHANNEL 5 /* ADC 通道 5 PA1*/ #define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/ #define CONVERT_BITS (1 << 12) /* 转换位数为12位 */ + static int adc_vol_sample(int argc, char *argv[]) { rt_adc_device_t adc_dev; @@ -55,3 +59,5 @@ static int adc_vol_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c index bfbd50095e..1133ad8d2b 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/can_sample.c @@ -18,7 +18,9 @@ #include #include "rtdevice.h" -#define CAN_DEV_NAME "can" /* CAN 设备名称 */ +#ifdef RT_USING_CAN + +#define CAN_DEV_NAME "can0" /* CAN 设备名称 */ static struct rt_semaphore rx_sem; /* 用于接收消息的信号量 */ static rt_device_t can_dev; /* CAN 设备句柄 */ @@ -142,3 +144,5 @@ int can_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(can_sample, can device sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c index e2e39664f3..025b4f26c0 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/hwtimer_sample.c @@ -17,6 +17,8 @@ #include #include +#ifdef RT_USING_HWTIMER + #define HWTIMER_DEV_NAME "timer0" /* 定时器名称 */ /* 定时器超时回调函数 */ @@ -83,3 +85,5 @@ static int hwtimer_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c index 4fd42baf41..c8a666609d 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -18,6 +30,8 @@ #include #include +#ifdef RT_USING_I2C + #define I2C_BUS_NAME "i2c0" /* I2C总线设备名称 */ #define SLAVE_ADDR 0x2D /* 从机地址 */ #define STR_LEN 16 /* 接收发送的数据长度 */ @@ -95,3 +109,5 @@ static void i2c_io_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(i2c_io_sample, i2c io sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c index b886876108..731dca4115 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -11,18 +23,26 @@ * 程序清单：这是一个 pm睡眠唤醒的使用例程 * 例程导出了 pm_sample 命令到控制终端 * 命令调用格式：pm_sample - * 命令解释：进入不同的睡眠模式，然后用按键唤醒 + * 命令解释：进入不同的睡眠模式，然后用按键唤醒。 * 程序功能：通过串口输出字符串，告知进入睡眠和唤醒睡眠的情况。 + * 注意：进入睡眠前，如果有中断挂起（SYSTICK、UART、EXTI等），睡眠将被瞬间唤醒。 */ #include #include -#include "drv_pm.h" +#include "drv_pm.h" +#include "ald_gpio.h" + + +#ifdef RT_USING_PM #define PM_NAME "pm" /* 设备名称 */ #define WAKE_UP_PIN 51 /* 唤醒源 */ #define SLEEP_TIMES 12 /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */ +/*部分芯片进入深度睡眠后，部分外设的部分寄存器可能会丢失*/ +#define SAVE_REG UART0 +#define SAVE_REG_TYPE UART_TypeDef struct pm_callback_t { @@ -64,14 +84,15 @@ void sleep_in_out_callback(rt_uint8_t event, rt_uint8_t mode, void *data) /*进入睡眠前*/ case RT_PM_ENTER_SLEEP: g_pm_data.flag = 1; rt_kprintf("\n\r##%d : ENTER ",g_pm_data.in_fun_times); - save_register(UART0,sizeof(UART_TypeDef),save_load_mem); /*备份寄存器的值*/ + /*进入深度睡眠后，部分外设的部分寄存器可能会丢失*/ + save_register(SAVE_REG,sizeof(SAVE_REG_TYPE),save_load_mem); /*备份寄存器的值*/ g_pm_data.in_fun_times++; /*进入睡眠次数+1*/ break; /*睡眠唤醒后*/ case RT_PM_EXIT_SLEEP: g_pm_data.flag = 0; /*睡眠唤醒后*/ - load_register(UART0,sizeof(UART_TypeDef),save_load_mem); /*还原寄存器的值*/ + load_register(SAVE_REG,sizeof(SAVE_REG_TYPE),save_load_mem); /*还原寄存器的值*/ rt_kprintf("\n\rEXIT\n\r"); - rt_pm_release(mode); /*释放休眠模式*/ + rt_pm_request(PM_SLEEP_MODE_NONE); /*进无休眠模式*/ return; default: break; @@ -118,7 +139,7 @@ static void pm_test(void *parameter) /*设置回调函数和私有数据*/ rt_pm_notify_set(sleep_in_out_callback,RT_NULL); - + while(i < SLEEP_TIMES) { @@ -130,9 +151,12 @@ static void pm_test(void *parameter) g_pm_data.flag = 2; } + + /*彻底释放无休眠模式*/ + rt_pm_release_all(PM_SLEEP_MODE_NONE); /*请求选择的休眠模式*/ - rt_pm_request(in_mode[i%6]); + rt_pm_request(in_mode[i%6]); rt_thread_mdelay(500); @@ -142,14 +166,19 @@ static void pm_test(void *parameter) rt_thread_mdelay(500); } - /*释放选择的休眠模式*/ - rt_pm_release(in_mode[i%6]); + /*释放选择的休眠模式 ，彻底释放*/ + rt_pm_release_all(in_mode[i%6]); i++; } - /*清除回调函数和私有数据*/ + + /*切换为无睡眠模式*/ + rt_pm_request(PM_SLEEP_MODE_NONE); + + /*清除回调函数和私有数据*/ rt_pm_notify_set(RT_NULL,RT_NULL); + rt_kprintf("thread pm_test close\n\r"); } @@ -187,3 +216,5 @@ static int pm_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(pm_sample, pm sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c index df82c1b41c..8d12b74e15 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c @@ -17,9 +17,12 @@ #include #include -#define LED_PIN_NUM 19 /* PF1 LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ + +#ifdef RT_USING_PWM + +#define LED_PIN_NUM 37 /* PF1 LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ #define PWM_DEV_NAME "pwm1" /* PWM设备名称 */ -#define PWM_DEV_CHANNEL 2 /* PA1 PWM通道 */ +#define PWM_DEV_CHANNEL 1 /* PWM通道 */ struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */ @@ -70,3 +73,5 @@ static int pwm_led_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(pwm_led_sample, pwm sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c index 711a3a0ebb..d66b9db9df 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/rtc_sample.c @@ -17,6 +17,8 @@ #include #include +#ifdef RT_USING_RTC + static int rtc_sample(int argc, char *argv[]) { rt_err_t ret = RT_EOK; @@ -39,7 +41,7 @@ static int rtc_sample(int argc, char *argv[]) } /* 延时3秒 */ - rt_thread_mdelay(3000); + rt_thread_mdelay(3000); /* 获取时间 */ now = time(RT_NULL); @@ -49,3 +51,5 @@ static int rtc_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(rtc_sample, rtc sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c index 994888cdb0..6f6e730288 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/spi_sample.c @@ -1,7 +1,19 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes @@ -17,13 +29,14 @@ #include #include +#ifdef RT_USING_SPI + #define SPI_DEVICE_NAME "spi00" #define BUF_LEN 16 static void spi_io_sample(int argc, char *argv[]) { struct rt_spi_device * spi_dev; /* spi设备的句柄 */ - struct rt_spi_configuration spi_config; rt_uint8_t i,buffer[BUF_LEN] = { 0U }; rt_err_t s_stat; rt_err_t result; @@ -37,23 +50,8 @@ static void spi_io_sample(int argc, char *argv[]) return; } - - /* 清空配置结构体 */ - rt_memset(&spi_config,0,sizeof(struct rt_spi_configuration)); - - spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ - spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ - spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ - spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ - spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ - spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ - - spi_config.data_width = 8; /* 数据长度：8 */ - - spi_config.max_hz = 2000000; /* 最快时钟频率 */ - /* 配置SPI设备 */ - s_stat = rt_spi_configure(spi_dev,&spi_config); + s_stat = rt_spi_configure(spi_dev,&(spi_dev->config)); if(s_stat != RT_EOK) { @@ -150,3 +148,5 @@ static void spi_io_sample(int argc, char *argv[]) } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(spi_io_sample, spi sample); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_adc.c b/bsp/essemi/es32f369x/drivers/drv_adc.c index 79afc06123..716fddcfa4 100644 --- a/bsp/essemi/es32f369x/drivers/drv_adc.c +++ b/bsp/essemi/es32f369x/drivers/drv_adc.c @@ -1,26 +1,44 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes * 2019-04-03 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include "board.h" -#include "drv_adc.h" -#include -#include +#include "drv_adc.h" #ifdef RT_USING_ADC /* define adc instance */ + +#ifdef BSP_USING_ADC0 static struct rt_adc_device _device_adc0; +#endif /*BSP_USING_ADC0*/ + +#ifdef BSP_USING_ADC1 +static struct rt_adc_device _device_adc1; +#endif /*BSP_USING_ADC1*/ /* enable or disable adc */ static rt_err_t es32f3_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) @@ -48,7 +66,8 @@ static adc_channel_t es32f3_adc_get_channel(rt_uint32_t channel) /* Initialize ADC pin */ gpio_initstruct.mode = GPIO_MODE_INPUT; - gpio_initstruct.pupd = GPIO_FLOATING; + gpio_initstruct.pupd = GPIO_FLOATING; + gpio_initstruct.odos = GPIO_OPEN_DRAIN; gpio_initstruct.podrv = GPIO_OUT_DRIVE_1; gpio_initstruct.nodrv = GPIO_OUT_DRIVE_1; gpio_initstruct.flt = GPIO_FILTER_DISABLE; @@ -60,77 +79,69 @@ static adc_channel_t es32f3_adc_get_channel(rt_uint32_t channel) { case 0: es32f3_channel = ADC_CHANNEL_0; - ald_gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH0_GPIO, ES_GPIO_ADC_CH0_PIN, &gpio_initstruct); break; case 1: es32f3_channel = ADC_CHANNEL_1; - ald_gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH1_GPIO, ES_GPIO_ADC_CH1_PIN, &gpio_initstruct); break; case 2: es32f3_channel = ADC_CHANNEL_2; - ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH2_GPIO, ES_GPIO_ADC_CH2_PIN, &gpio_initstruct); break; case 3: es32f3_channel = ADC_CHANNEL_3; - ald_gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH3_GPIO, ES_GPIO_ADC_CH3_PIN, &gpio_initstruct); break; case 4: es32f3_channel = ADC_CHANNEL_4; - ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH4_GPIO, ES_GPIO_ADC_CH4_PIN, &gpio_initstruct); break; case 5: es32f3_channel = ADC_CHANNEL_5; - ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH5_GPIO, ES_GPIO_ADC_CH5_PIN, &gpio_initstruct); break; case 6: es32f3_channel = ADC_CHANNEL_6; - ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH6_GPIO, ES_GPIO_ADC_CH6_PIN, &gpio_initstruct); break; case 7: es32f3_channel = ADC_CHANNEL_7; - ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH7_GPIO, ES_GPIO_ADC_CH7_PIN, &gpio_initstruct); break; case 8: es32f3_channel = ADC_CHANNEL_8; - ald_gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH8_GPIO, ES_GPIO_ADC_CH8_PIN, &gpio_initstruct); break; case 9: es32f3_channel = ADC_CHANNEL_9; - ald_gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH9_GPIO, ES_GPIO_ADC_CH9_PIN, &gpio_initstruct); break; case 10: es32f3_channel = ADC_CHANNEL_10; - ald_gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH10_GPIO, ES_GPIO_ADC_CH10_PIN, &gpio_initstruct); break; case 11: es32f3_channel = ADC_CHANNEL_11; - ald_gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH11_GPIO, ES_GPIO_ADC_CH11_PIN, &gpio_initstruct); break; case 12: es32f3_channel = ADC_CHANNEL_12; - ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH12_GPIO, ES_GPIO_ADC_CH12_PIN, &gpio_initstruct); break; case 13: es32f3_channel = ADC_CHANNEL_13; - ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH13_GPIO, ES_GPIO_ADC_CH13_PIN, &gpio_initstruct); break; case 14: es32f3_channel = ADC_CHANNEL_14; - ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(ES_GPIO_ADC_CH14_GPIO, ES_GPIO_ADC_CH14_PIN, &gpio_initstruct); break; case 15: es32f3_channel = ADC_CHANNEL_15; - ald_gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct); - break; - case 16: - es32f3_channel = ADC_CHANNEL_16; - break; - case 17: - es32f3_channel = ADC_CHANNEL_17; - break; - case 18: - es32f3_channel = ADC_CHANNEL_18; + ald_gpio_init(ES_GPIO_ADC_CH15_GPIO, ES_GPIO_ADC_CH15_PIN, &gpio_initstruct); break; + default: break; } @@ -149,7 +160,7 @@ static rt_err_t es32f3_get_adc_value(struct rt_adc_device *device, rt_uint32_t c /* config adc channel */ nm_config.ch = es32f3_adc_get_channel(channel); nm_config.idx = ADC_NCH_IDX_1; - nm_config.samp = ADC_SAMPLETIME_4; + nm_config.samp = ES_ADC0_NCH_SAMPLETIME; ald_adc_normal_channel_config(_hadc, &nm_config); ald_adc_normal_start(_hadc); @@ -169,23 +180,51 @@ static const struct rt_adc_ops es32f3_adc_ops = int rt_hw_adc_init(void) { int result = RT_EOK; - static adc_handle_t _h_adc0; + adc_handle_t _h_adc; /* adc function initialization */ + _h_adc.init.scan = DISABLE; + _h_adc.init.cont = DISABLE; + _h_adc.init.disc = ADC_ALL_DISABLE; + _h_adc.init.disc_nr = ADC_DISC_NR_1; + _h_adc.init.nch_nr = ADC_NCH_NR_16; + _h_adc.init.nche_sel = ADC_NCHESEL_MODE_ALL; + _h_adc.init.cont = DISABLE; + _h_adc.init.n_ref = ADC_NEG_REF_VSS; + _h_adc.init.p_ref = ADC_POS_REF_VDD; + +#ifdef BSP_USING_ADC0 + + static adc_handle_t _h_adc0; + + _h_adc0.init = _h_adc.init; + _h_adc0.perh = ADC0; - _h_adc0.init.align = ADC_DATAALIGN_RIGHT; - _h_adc0.init.scan = DISABLE; - _h_adc0.init.cont = DISABLE; - _h_adc0.init.disc = ADC_ALL_DISABLE; - _h_adc0.init.disc_nr = ADC_DISC_NR_1; - _h_adc0.init.data_bit = ADC_CONV_BIT_12; - _h_adc0.init.div = ADC_CKDIV_128; - _h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL; - _h_adc0.init.n_ref = ADC_NEG_REF_VSS; - _h_adc0.init.p_ref = ADC_POS_REF_VDD; + _h_adc0.init.align = ES_ADC0_ALIGN; + _h_adc0.init.data_bit = ES_ADC0_DATA_BIT; + _h_adc0.init.div = ES_ADC0_CLK_DIV; ald_adc_init(&_h_adc0); - - rt_hw_adc_register(&_device_adc0, "adc0", &es32f3_adc_ops, &_h_adc0); + + rt_hw_adc_register(&_device_adc0, ES_DEVICE_NAME_ADC0, &es32f3_adc_ops, &_h_adc0); + +#endif /*BSP_USING_ADC0*/ + +#ifdef BSP_USING_ADC1 + + static adc_handle_t _h_adc1; + + _h_adc1.init = _h_adc.init; + + _h_adc1.perh = ADC1; + _h_adc1.init.align = ES_ADC1_ALIGN; + _h_adc1.init.data_bit = ES_ADC1_DATA_BIT; + _h_adc1.init.div = ES_ADC1_CLK_DIV; + ald_adc_init(&_h_adc1); + + rt_hw_adc_register(&_device_adc1, ES_DEVICE_NAME_ADC1, &es32f3_adc_ops, &_h_adc1); + +#endif /*BSP_USING_ADC1*/ + return result; } diff --git a/bsp/essemi/es32f369x/drivers/drv_adc.h b/bsp/essemi/es32f369x/drivers/drv_adc.h index eaddd67407..6585b44cf0 100644 --- a/bsp/essemi/es32f369x/drivers/drv_adc.h +++ b/bsp/essemi/es32f369x/drivers/drv_adc.h @@ -3,14 +3,29 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-04-03 wangyq the first version + * 2019-04-03 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_ADC_H__ #define DRV_ADC_H__ +#include "es_conf_info_adc.h" + int rt_hw_adc_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_can.c b/bsp/essemi/es32f369x/drivers/drv_can.c index 04f4f161d7..6e7456b9b6 100644 --- a/bsp/essemi/es32f369x/drivers/drv_can.c +++ b/bsp/essemi/es32f369x/drivers/drv_can.c @@ -1,51 +1,93 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include "drv_can.h" -#ifdef BSP_USING_CAN +#ifdef RT_USING_CAN static struct es32f3_can can; -/* attention !!! baud calculation example: Pclk / ((sjw + seg1 + seg2) * psc) 48 / ((1 + 3 + 2) * 8) = 1MHz */ -static const struct es32f3_baud_rate_tab can_baud_rate_tab[] = -{ - {CAN1MBaud, 8}, - {CAN800kBaud, 10}, - {CAN500kBaud, 16}, - {CAN250kBaud, 32}, - {CAN125kBaud, 64}, - {CAN100kBaud, 80}, - {CAN50kBaud, 160}, - {CAN20kBaud, 400}, - {CAN10kBaud, 800} -}; - -static rt_uint32_t get_can_baud_index(rt_uint32_t baud) -{ - rt_uint32_t len, index; - len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]); - for (index = 0; index < len; index++) +static rt_uint32_t get_can_baud_index(rt_uint32_t baud,can_init_t * init) +{ +/* attention !!! baud calculation example: Pclk / ((1 + seg1 + seg2) * psc) Pclk=48 / ((1 + seg1=3 + seg2=2) * 8) = 1MHz */ + double target,temp,min; + uint32_t i,j,j_max,near = 0; + target = (double)(ald_cmu_get_pclk1_clock()); + target/= baud; /*计算误差1*/ + + min = 0xFFFFFFFF; + + for(i = 1 + 16 + 8 ;i > 2;i--) /*SYNC_SEG + SEG1 + SEG2*/ { - if (can_baud_rate_tab[index].baud_rate == baud) - return index; + j_max = target/i/(0.98) + 1; /*缩小范围*/ + j_max = (j_max > 1024) ? (1024) : (j_max); + + for(j = target/i/1.02 ;j < j_max;j++) + { + temp = target/i/j; /*计算误差2*/ + temp = (temp > 1) ? (temp - 1) : (1 - temp); + temp+= ((1.0 * i * j) / 0xFFFFFFFF) ; + + if(temp < min) + { + if(temp > 0.000001) + { + near = (i<<16) + j; + min = temp; + } + else + { + init->seg1 = (can_seg1_t)((i - 1)*2/3-1); + init->seg2 = (can_seg2_t)(i - init->seg1 - 1 - 1 - 1); + init->psc = j; + + return 0; + } + } + } } - return 0; /* default baud is CAN1MBaud */ + if(min < 0.01) + { + i = near>>16; + j = near % (1<<16); + init->seg1 = (can_seg1_t)((i - 1)*2/3-1); + init->seg2 = (can_seg2_t)(i - init->seg1 - 1 - 1 - 1); + init->psc = j; + + return 0; + } + else + { + return 1; + } } + static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configure *cfg) { struct es32f3_can *drv_can; - rt_uint32_t baud_index; RT_ASSERT(can_device); RT_ASSERT(cfg); @@ -56,7 +98,7 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu drv_can->CanHandle.init.ttcm = DISABLE; drv_can->CanHandle.init.abom = ENABLE; drv_can->CanHandle.init.awk = DISABLE; - drv_can->CanHandle.init.artx = DISABLE; + drv_can->CanHandle.init.artx = (type_func_t)ES_CAN0_AUTO_BAN_RE_T; drv_can->CanHandle.init.rfom = DISABLE; drv_can->CanHandle.init.txmp = ENABLE; @@ -75,12 +117,13 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu drv_can->CanHandle.init.mode = CAN_MODE_SILENT_LOOPBACK; break; } - - baud_index = get_can_baud_index(cfg->baud_rate); - drv_can->CanHandle.init.sjw = CAN_SJW_1; - drv_can->CanHandle.init.seg1 = CAN_SEG1_3; - drv_can->CanHandle.init.seg2 = CAN_SEG2_2; - drv_can->CanHandle.init.psc = can_baud_rate_tab[baud_index].config_data; + /*配置参数*/ + if(get_can_baud_index(cfg->baud_rate,&(drv_can->CanHandle.init))) + { + return -RT_ERROR; + } + drv_can->CanHandle.init.sjw = (can_sjw_t)(cfg->reserved); + /* init can */ if (ald_can_init(&drv_can->CanHandle) != OK) { @@ -95,8 +138,12 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *arg) { rt_uint32_t argval; + struct es32f3_can *drv_can; + +#ifdef RT_CAN_USING_HDR struct rt_can_filter_config *filter_cfg; +#endif RT_ASSERT(can_device != RT_NULL); drv_can = (struct es32f3_can *)can_device->parent.user_data; @@ -108,17 +155,24 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar argval = (rt_uint32_t) arg; if (argval == RT_DEVICE_FLAG_INT_RX) { - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 | - CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV0, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP1, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF1, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV1, DISABLE); } else if (argval == RT_DEVICE_FLAG_INT_TX) { ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_TXM, DISABLE); } else if (argval == RT_DEVICE_CAN_INT_ERR) - { - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | - CAN_IT_PRERR | CAN_IT_ERR), DISABLE); + { + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_ERR, DISABLE); } break; case RT_DEVICE_CTRL_SET_INT: @@ -127,29 +181,36 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar { NVIC_SetPriority(CAN0_RX0_IRQn, 1); NVIC_EnableIRQ(CAN0_RX0_IRQn); - - NVIC_SetPriority(CAN0_RX0_IRQn, 1); - NVIC_EnableIRQ(CAN0_RX0_IRQn); - - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 | - CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), ENABLE); + + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV0, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP1, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF1, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV1, ENABLE); + } else if (argval == RT_DEVICE_FLAG_INT_TX) { NVIC_SetPriority(CAN0_TX_IRQn, 1); NVIC_EnableIRQ(CAN0_TX_IRQn); - + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_TXM, ENABLE); } else if (argval == RT_DEVICE_CAN_INT_ERR) { NVIC_SetPriority(CAN0_EXCEPTION_IRQn, 1); NVIC_EnableIRQ(CAN0_EXCEPTION_IRQn); - - ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | - CAN_IT_PRERR | CAN_IT_ERR), ENABLE); + + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_ERR, ENABLE); + } break; +#ifdef RT_CAN_USING_HDR case RT_CAN_CMD_SET_FILTER: if (RT_NULL == arg) { @@ -161,20 +222,70 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar filter_cfg = (struct rt_can_filter_config *)arg; /* get default filter */ for (int i = 0; i < filter_cfg->count; i++) - { - drv_can->FilterConfig.number = filter_cfg->items[i].hdr; + { + + /*默认过滤表判断*/ + if(filter_cfg->items[i].hdr < drv_can->device.config.maxhdr) + drv_can->FilterConfig.number = filter_cfg->items[i].hdr; + else + drv_can->FilterConfig.number = ES_C_CAN_DEFAULT_FILTER_NUMBER; + + if(filter_cfg->items[i].mode) + { + /*标识符列表模式： 类型匹配 ，id匹配为：接收的id = 配置的id + 或者 = 配置的mask ，通过*/ + /*扩展帧*/ + if(filter_cfg->items[i].ide) + { +// filter_cfg->items[i].id = filter_cfg->items[i].id ; /*id 29 位*/ + filter_cfg->items[i].mask = ((filter_cfg->items[i].mask << 3) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)); + } + else /*标准帧*/ + { + filter_cfg->items[i].id = (filter_cfg->items[i].id << 18); + filter_cfg->items[i].mask = ((filter_cfg->items[i].mask << 21) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)); + } + } + else + { + /*标识符掩码模式*/ + /*扩展帧*/ + if(filter_cfg->items[i].ide) + { + filter_cfg->items[i].mask = (filter_cfg->items[i].mask)<<3; + } + else /*标准帧*/ + { + filter_cfg->items[i].id = (filter_cfg->items[i].id)<<18; + filter_cfg->items[i].mask = (filter_cfg->items[i].mask)<<21; + } + +#if ES_C_CAN_FILTER_FRAME_TYPE + /*匹配类型*/ + filter_cfg->items[i].mask |= 0x6; +#endif + + } + drv_can->FilterConfig.id_high = (filter_cfg->items[i].id >> 13) & 0xFFFF; drv_can->FilterConfig.id_low = ((filter_cfg->items[i].id << 3) | (filter_cfg->items[i].ide << 2) | (filter_cfg->items[i].rtr << 1)) & 0xFFFF; drv_can->FilterConfig.mask_id_high = (filter_cfg->items[i].mask >> 16) & 0xFFFF; drv_can->FilterConfig.mask_id_low = filter_cfg->items[i].mask & 0xFFFF; + drv_can->FilterConfig.mode = (can_filter_mode_t)filter_cfg->items[i].mode; /* Filter conf */ ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig); } } break; + +#endif case RT_CAN_CMD_SET_MODE: argval = (rt_uint32_t) arg; if (argval != RT_CAN_MODE_NORMAL && @@ -192,18 +303,7 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar break; case RT_CAN_CMD_SET_BAUD: argval = (rt_uint32_t) arg; - if (argval != CAN1MBaud && - argval != CAN800kBaud && - argval != CAN500kBaud && - argval != CAN250kBaud && - argval != CAN125kBaud && - argval != CAN100kBaud && - argval != CAN50kBaud && - argval != CAN20kBaud && - argval != CAN10kBaud) - { - return -RT_ERROR; - } + if (argval != drv_can->device.config.baud_rate) { drv_can->device.config.baud_rate = argval; @@ -312,6 +412,7 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t } /* clear TIR */ h_can->perh->TxMailBox[box_num].TXID &= CAN_TXID0_TXMREQ_MSK; + /* Set up the Id */ if (RT_CAN_STDID == pmsg->ide) { @@ -336,7 +437,7 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t ((uint32_t)pmsg->data[0] << CAN_TXDL0_BYTE0_POSS)); /* Request transmission */ SET_BIT(h_can->perh->TxMailBox[box_num].TXID, CAN_TXID0_TXMREQ_MSK); - + return RT_EOK; } else @@ -346,6 +447,8 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t return -RT_ERROR; } + + } static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) @@ -427,8 +530,12 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) /* RX interrupt */ else { + if(CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO0) != 0) + { /* save to user list */ rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + } + /* Clear FIFO0 rx Flag */ SET_BIT(h_can->perh->RXF0, CAN_RXF0_FREE_MSK); } @@ -444,8 +551,12 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) /* RX interrupt */ else { + if(CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO1) != 0) + { /* save to user list */ rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + } + /* Clear FIFO0 rx Flag */ SET_BIT(h_can->perh->RXF1, CAN_RXF1_FREE_MSK); } @@ -575,30 +686,30 @@ void CAN0_EXCEPTION_Handler(void) int rt_hw_can_init(void) { gpio_init_t h_gpio; - struct can_configure config = CANDEFAULTCONFIG; - - config.privmode = RT_CAN_MODE_NOPRIV; - config.ticks = 50; -#ifdef RT_CAN_USING_HDR - config.maxhdr = 14; -#endif /* Initialize can common pin */ h_gpio.odos = GPIO_PUSH_PULL; h_gpio.pupd = GPIO_PUSH_UP; - h_gpio.podrv = GPIO_OUT_DRIVE_1; - h_gpio.nodrv = GPIO_OUT_DRIVE_0_1; + h_gpio.podrv = GPIO_OUT_DRIVE_6; + h_gpio.nodrv = GPIO_OUT_DRIVE_6; h_gpio.flt = GPIO_FILTER_DISABLE; h_gpio.type = GPIO_TYPE_TTL; - h_gpio.func = GPIO_FUNC_3; +#if defined(ES_CAN0_RX_GPIO_FUNC)&&defined(ES_CAN0_RX_GPIO_PORT)&&defined(ES_CAN0_RX_GPIO_PIN) /* Initialize can rx pin */ - h_gpio.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_8, &h_gpio); - + h_gpio.mode = GPIO_MODE_INPUT; + h_gpio.func = ES_CAN0_RX_GPIO_FUNC; + ald_gpio_init(ES_CAN0_RX_GPIO_PORT, ES_CAN0_RX_GPIO_PIN, &h_gpio); +#endif + + +#if defined(ES_CAN0_TX_GPIO_FUNC)&&defined(ES_CAN0_TX_GPIO_PORT)&&defined(ES_CAN0_TX_GPIO_PIN) /* Initialize can tx pin */ - h_gpio.mode = GPIO_MODE_OUTPUT; - ald_gpio_init(GPIOB, GPIO_PIN_9, &h_gpio); + h_gpio.mode = GPIO_MODE_OUTPUT; + h_gpio.func = ES_CAN0_TX_GPIO_FUNC; + ald_gpio_init(ES_CAN0_TX_GPIO_PORT, ES_CAN0_TX_GPIO_PIN, &h_gpio); +#endif + /* config default filter */ can_filter_t filter = {0}; @@ -607,15 +718,21 @@ int rt_hw_can_init(void) filter.mask_id_high = 0x0000; filter.mask_id_low = 0x0000; filter.fifo = CAN_FILTER_FIFO0; - filter.number = 0; + filter.number = ES_C_CAN_DEFAULT_FILTER_NUMBER; filter.mode = CAN_FILTER_MODE_MASK; filter.scale = CAN_FILTER_SCALE_32; filter.active = ENABLE; can.FilterConfig = filter; - can.device.config = config; + can.device.config = (struct can_configure)ES_CAN0_CONFIG; +#ifdef RT_CAN_USING_HDR + can.device.config.maxhdr = 14; +#endif + can.device.config.privmode = RT_CAN_MODE_NOPRIV; + can.device.config.ticks = 50; + can.device.config.reserved = ES_CAN0_SJW; /* register CAN1 device */ - rt_hw_can_register(&can.device, "can", &_can_ops, &can); + rt_hw_can_register(&can.device, ES_DEVICE_NAME_CAN0, &_can_ops, &can); return 0; } diff --git a/bsp/essemi/es32f369x/drivers/drv_can.h b/bsp/essemi/es32f369x/drivers/drv_can.h index cffe4b81b0..d7eeb859aa 100644 --- a/bsp/essemi/es32f369x/drivers/drv_can.h +++ b/bsp/essemi/es32f369x/drivers/drv_can.h @@ -3,9 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_CAN_H__ @@ -14,16 +27,9 @@ #include #include #include +#include "es_conf_info_can.h" -#include -#include - -struct es32f3_baud_rate_tab -{ - rt_uint32_t baud_rate; - rt_uint32_t config_data; -}; - +#ifdef RT_USING_CAN /* es32f3 can device */ struct es32f3_can { @@ -34,4 +40,5 @@ struct es32f3_can int rt_hw_can_init(void); +#endif #endif /*DRV_CAN_H__ */ diff --git a/bsp/essemi/es32f369x/drivers/drv_gpio.c b/bsp/essemi/es32f369x/drivers/drv_gpio.c index fa39a31ea5..8ce6ab7aa8 100644 --- a/bsp/essemi/es32f369x/drivers/drv_gpio.c +++ b/bsp/essemi/es32f369x/drivers/drv_gpio.c @@ -1,107 +1,40 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ -#include -#include #include "board.h" #include "drv_gpio.h" -#include -#include -#ifdef RT_USING_PIN +/*管脚映射在 es_conf_info_map.h 的 pins[] 中*/ -#define __ES32F3_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index} -#define __ES32F3_PIN_DEFAULT {-1, 0, 0} - -/* ES32F3 GPIO driver */ -struct pin_index -{ - int index; - GPIO_TypeDef *gpio; - uint32_t pin; -}; +#ifdef RT_USING_PIN -static const struct pin_index pins[] = -{ - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(2, C, 13), - __ES32F3_PIN(3, C, 14), - __ES32F3_PIN(4, C, 15), - __ES32F3_PIN(5, H, 0), - __ES32F3_PIN(6, H, 1), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(8, C, 0), - __ES32F3_PIN(9, C, 1), - __ES32F3_PIN(10, C, 2), - __ES32F3_PIN(11, C, 3), - __ES32F3_PIN(12, H, 3), - __ES32F3_PIN(13, H, 4), - __ES32F3_PIN(14, A, 0), - __ES32F3_PIN(15, A, 1), - __ES32F3_PIN(16, A, 2), - __ES32F3_PIN(17, A, 3), - __ES32F3_PIN(18, F, 0), - __ES32F3_PIN(19, F, 1), - __ES32F3_PIN(20, A, 4), - __ES32F3_PIN(21, A, 5), - __ES32F3_PIN(22, A, 6), - __ES32F3_PIN(23, A, 7), - __ES32F3_PIN(24, C, 4), - __ES32F3_PIN(25, C, 5), - __ES32F3_PIN(26, B, 0), - __ES32F3_PIN(27, B, 1), - __ES32F3_PIN(28, B, 2), - __ES32F3_PIN(29, B, 10), - __ES32F3_PIN(30, B, 11), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(33, B, 12), - __ES32F3_PIN(34, B, 13), - __ES32F3_PIN(35, B, 14), - __ES32F3_PIN(36, B, 15), - __ES32F3_PIN(37, C, 6), - __ES32F3_PIN(38, C, 7), - __ES32F3_PIN(39, C, 8), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(46, A, 13), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN(49, A, 14), - __ES32F3_PIN(50, A, 15), - __ES32F3_PIN(51, C, 10), - __ES32F3_PIN(52, C, 11), - __ES32F3_PIN(53, C, 12), - __ES32F3_PIN(54, D, 2), - __ES32F3_PIN(55, B, 3), - __ES32F3_PIN(56, B, 4), - __ES32F3_PIN(57, B, 5), - __ES32F3_PIN(58, B, 6), - __ES32F3_PIN(59, B, 7), - __ES32F3_PIN(60, H, 2), - __ES32F3_PIN(61, B, 8), - __ES32F3_PIN(62, B, 9), - __ES32F3_PIN_DEFAULT, - __ES32F3_PIN_DEFAULT, -}; struct pin_irq_map { rt_uint16_t pinbit; IRQn_Type irqno; }; + static const struct pin_irq_map pin_irq_map[] = { {GPIO_PIN_0, EXTI0_IRQn}, @@ -140,7 +73,151 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] = { -1, 0, RT_NULL, RT_NULL}, { -1, 0, RT_NULL, RT_NULL}, { -1, 0, RT_NULL, RT_NULL}, -}; +}; + +#ifdef ES_CONF_EXTI_IRQ_0 + +RT_WEAK void irq_pin0_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 0\r\n"); +} +#endif + +#ifdef ES_CONF_EXTI_IRQ_1 + +RT_WEAK void irq_pin1_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 1\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_2 + + RT_WEAK void irq_pin2_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 2\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_3 + +RT_WEAK void irq_pin3_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 3\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_4 + +RT_WEAK void irq_pin4_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 4\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_5 + +RT_WEAK void irq_pin5_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 5\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_6 + +RT_WEAK void irq_pin6_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 6\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_7 + +RT_WEAK void irq_pin7_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 7\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_8 + +RT_WEAK void irq_pin8_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 8\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_9 + +RT_WEAK void irq_pin9_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 9\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_10 + +RT_WEAK void irq_pin10_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 10\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_11 + +RT_WEAK void irq_pin11_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 11\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_12 + +RT_WEAK void irq_pin12_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 12\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_13 + +RT_WEAK void irq_pin13_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 13\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_14 + +RT_WEAK void irq_pin14_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 14\r\n"); +} + +#endif + +#ifdef ES_CONF_EXTI_IRQ_15 + +RT_WEAK void irq_pin15_callback(void* arg) +{ + rt_kprintf("\r\nEXTI 15\r\n"); +} + +#endif + #define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) const struct pin_index *get_pin(uint8_t pin) @@ -200,8 +277,8 @@ void es32f3_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) gpio_initstruct.podrv = GPIO_OUT_DRIVE_1; gpio_initstruct.nodrv = GPIO_OUT_DRIVE_0_1; gpio_initstruct.type = GPIO_TYPE_CMOS; - gpio_initstruct.pupd = GPIO_FLOATING; - gpio_initstruct.odos = GPIO_PUSH_PULL; + gpio_initstruct.odos = GPIO_PUSH_PULL; + gpio_initstruct.flt = GPIO_FILTER_DISABLE; if (mode == PIN_MODE_OUTPUT) { @@ -364,7 +441,11 @@ rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin, ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct); /* Configure GPIO_InitStructure */ gpio_initstruct.mode = GPIO_MODE_INPUT; - gpio_initstruct.func = GPIO_FUNC_1; + gpio_initstruct.odos = GPIO_PUSH_PULL; + gpio_initstruct.podrv = GPIO_OUT_DRIVE_1; + gpio_initstruct.nodrv = GPIO_OUT_DRIVE_1; + gpio_initstruct.func = GPIO_FUNC_1; + gpio_initstruct.flt = GPIO_FILTER_DISABLE; switch (pin_irq_hdr_tab[irqindex].mode) { case PIN_IRQ_MODE_RISING: @@ -408,18 +489,9 @@ const static struct rt_pin_ops _es32f3_pin_ops = es32f3_pin_attach_irq, es32f3_pin_detach_irq, es32f3_pin_irq_enable, - RT_NULL, + /*RT_NULL,*/ }; -int rt_hw_pin_init(void) -{ - int result; - ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); - result = rt_device_pin_register("pin", &_es32f3_pin_ops, RT_NULL); - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) { uint16_t irqno; @@ -560,4 +632,44 @@ void EXTI15_Handler(void) rt_interrupt_leave(); } +int rt_hw_pin_init(void) +{ + int result; + + +#ifdef ES_INIT_GPIOS + + rt_size_t i,gpio_conf_num = sizeof(gpio_conf_all) / sizeof(gpio_conf_t); + +#endif + + ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); + + result = rt_device_pin_register(ES_DEVICE_NAME_PIN, &_es32f3_pin_ops, RT_NULL); + + if(result != RT_EOK)return result; + +#ifdef ES_INIT_GPIOS + + for(i = 0;i < gpio_conf_num;i++) + { + rt_pin_mode( gpio_conf_all[i].pin,gpio_conf_all[i].pin_mode); + + if((gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT)||(gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT_OD)) + rt_pin_write(gpio_conf_all[i].pin,gpio_conf_all[i].pin_level); + + if(!gpio_conf_all[i].irq_en)continue; + + rt_pin_attach_irq(gpio_conf_all[i].pin, gpio_conf_all[i].irq_mode, gpio_conf_all[i].callback, RT_NULL); + rt_pin_irq_enable(gpio_conf_all[i].pin, gpio_conf_all[i].irq_en); + } + +#endif + + + + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_gpio.h b/bsp/essemi/es32f369x/drivers/drv_gpio.h index fef8fb8487..8489e625d5 100644 --- a/bsp/essemi/es32f369x/drivers/drv_gpio.h +++ b/bsp/essemi/es32f369x/drivers/drv_gpio.h @@ -3,14 +3,29 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_GPIO_H__ #define DRV_GPIO_H__ +#include "es_conf_info_gpio.h" + int rt_hw_pin_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_hwtimer.c b/bsp/essemi/es32f369x/drivers/drv_hwtimer.c index f693137ae7..e0fd46a36b 100644 --- a/bsp/essemi/es32f369x/drivers/drv_hwtimer.c +++ b/bsp/essemi/es32f369x/drivers/drv_hwtimer.c @@ -1,21 +1,33 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes * 2019-3-19 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include -#include -#include -#include +#include + #ifdef RT_USING_HWTIMER @@ -26,53 +38,167 @@ struct es32f3_hwtimer_dev IRQn_Type IRQn; }; -#ifdef BSP_USING_HWTIMER0 -static struct es32f3_hwtimer_dev hwtimer0; +#ifdef BSP_USING_AD16C4T0_HWTIMER +static struct es32f3_hwtimer_dev ad16c4t0_hwtimer; -void BS16T0_Handler(void) +static struct rt_hwtimer_info ad16c4t0_info = { - ald_timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer0.parent); + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_AD16C4T0_HWTIMER_MODE +}; - if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode) - { - ald_timer_base_stop(hwtimer0.hwtimer_periph); - } +void AD16C4T0_UP_Handler(void) +{ + ald_timer_clear_flag_status(ad16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&ad16c4t0_hwtimer.parent); } + #endif -#ifdef BSP_USING_HWTIMER1 -static struct es32f3_hwtimer_dev hwtimer1; -/* can not use when UART2 Handler is enabled */ -void BS16T1_Handler(void) +#ifdef BSP_USING_AD16C4T1_HWTIMER + +static struct es32f3_hwtimer_dev ad16c4t1_hwtimer; + +static struct rt_hwtimer_info ad16c4t1_info = { - /* if BS16T1 it */ - if (ald_timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) && - ald_timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE)) - { - ald_timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer1.parent); + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_AD16C4T1_HWTIMER_MODE +}; - if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) - { - ald_timer_base_stop(hwtimer1.hwtimer_periph); - } - } +void AD16C4T1_UP_Handler(void) +{ + ald_timer_clear_flag_status(ad16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&ad16c4t1_hwtimer.parent); } + #endif +#ifdef BSP_USING_GP32C4T0_HWTIMER + +static struct es32f3_hwtimer_dev gp32c4t0_hwtimer; -static struct rt_hwtimer_info es32f3_hwtimer_info = +static struct rt_hwtimer_info gp32c4t0_info = { - 96000000, /* maximum count frequency */ - 1, /* minimum count frequency */ - 65535, /* counter maximum value */ - HWTIMER_CNTMODE_UP + + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV , /* maximum count frequency */ + ( ES_SYS_CLK >> ES_CMU_PCLK_1_DIV )/(1U<<16), /* minimum count frequency */ + 0xFFFFFFFF, /* counter maximum value */ + ES_GP32C4T0_HWTIMER_MODE }; +void GP32C4T0_Handler(void) +{ + ald_timer_clear_flag_status(gp32c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp32c4t0_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_GP32C4T1_HWTIMER + +static struct es32f3_hwtimer_dev gp32c4t1_hwtimer; + +static struct rt_hwtimer_info gp32c4t1_info = +{ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV ), /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV )/(1U<<16), /* minimum count frequency */ + 0xFFFFFFFF, /* counter maximum value */ + ES_GP32C4T1_HWTIMER_MODE +}; + +void GP32C4T1_Handler(void) +{ + ald_timer_clear_flag_status(gp32c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp32c4t1_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_GP16C4T0_HWTIMER + +static struct es32f3_hwtimer_dev gp16c4t0_hwtimer; + +static struct rt_hwtimer_info gp16c4t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C4T0_HWTIMER_MODE +}; + +void GP16C4T0_Handler(void) +{ + ald_timer_clear_flag_status(gp16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c4t0_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_GP16C4T1_HWTIMER + +static struct es32f3_hwtimer_dev gp16c4t1_hwtimer; + +static struct rt_hwtimer_info gp16c4t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C4T1_HWTIMER_MODE +}; + +void GP16C4T1_Handler(void) +{ + ald_timer_clear_flag_status(gp16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&gp16c4t1_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_BS16T0_HWTIMER + +static struct es32f3_hwtimer_dev bs16t0_hwtimer; + +static struct rt_hwtimer_info bs16t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T0_HWTIMER_MODE +}; + +void BS16T0_Handler(void) +{ + ald_timer_clear_flag_status(bs16t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t0_hwtimer.parent); +} + +#endif +#ifdef BSP_USING_BS16T1_HWTIMER + +static struct es32f3_hwtimer_dev bs16t1_hwtimer; + +static struct rt_hwtimer_info bs16t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T1_HWTIMER_MODE +}; + +void BS16T1_Handler(void) +{ + ald_timer_clear_flag_status(bs16t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); + rt_device_hwtimer_isr(&bs16t1_hwtimer.parent); +} + +#endif + static void es32f3_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) { struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + struct rt_hwtimer_info *hwtimer_info = (struct rt_hwtimer_info *)timer->info; + + RT_ASSERT(hwtimer != RT_NULL); if (1 == state) @@ -81,19 +207,21 @@ static void es32f3_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE); NVIC_EnableIRQ(hwtimer->IRQn); } - hwtimer->parent.freq = ald_cmu_get_pclk1_clock(); - es32f3_hwtimer_info.maxfreq = ald_cmu_get_pclk1_clock(); - es32f3_hwtimer_info.minfreq = ald_cmu_get_pclk1_clock(); + + hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); + hwtimer_info->maxfreq = hwtimer->parent.freq; + hwtimer_info->minfreq = (hwtimer->parent.freq)/0xFFFF; + } static rt_err_t es32f3_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) { - struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; RT_ASSERT(hwtimer != RT_NULL); - + WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt); ald_timer_base_start(hwtimer->hwtimer_periph); @@ -135,10 +263,37 @@ static rt_err_t es32f3_hwtimer_control(rt_hwtimer_t *timer, { case HWTIMER_CTRL_FREQ_SET: freq = *(rt_uint32_t *)args; - if (freq != ald_cmu_get_pclk1_clock()) - { - ret = -RT_ERROR; + + ret = -RT_ERROR; + + if(freq) + { + double temp,target; + temp = (double)ald_cmu_get_pclk1_clock(); + target = temp/freq; + + if(target < 0x10001) /*最大分频 = max(PRES)+1*/ + { + temp = target - (int)(target); + + if((temp > 0.998)&&(target < 0x10000)) + { + hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target; + ret = RT_EOK; + } + if((temp < 0.002)&&(target >= 0x1)) + { + hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target - 1; + ret = RT_EOK; + } + + } + + if(ret == RT_EOK) /*更新信息*/ + hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); + } + break; case HWTIMER_CTRL_STOP: @@ -166,24 +321,124 @@ int rt_hw_hwtimer_init(void) { rt_err_t ret = RT_EOK; -#ifdef BSP_USING_HWTIMER0 - static timer_handle_t _hwtimer_periph0; - _hwtimer_periph0.perh = BS16T0; - hwtimer0.IRQn = BS16T0_IRQn; - hwtimer0.hwtimer_periph = &_hwtimer_periph0; - hwtimer0.parent.info = &es32f3_hwtimer_info; - hwtimer0.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer0.parent, "timer0", &hwtimer0); -#endif - -#ifdef BSP_USING_HWTIMER1 - static timer_handle_t _hwtimer_periph1; - _hwtimer_periph1.perh = BS16T1; - hwtimer1.IRQn = BS16T1_IRQn; - hwtimer1.hwtimer_periph = &_hwtimer_periph1; - hwtimer1.parent.info = &es32f3_hwtimer_info; - hwtimer1.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1); +#ifdef BSP_USING_AD16C4T0_HWTIMER + static timer_handle_t ad16c4t0_hwtimer_periph; + + ad16c4t0_hwtimer_periph.perh = AD16C4T0; + ad16c4t0_hwtimer.IRQn = AD16C4T0_UP_IRQn; + + ad16c4t0_hwtimer_periph.init.prescaler = ES_AD16C4T0_HWTIMER_PRES - 1; + ad16c4t0_hwtimer_periph.init.mode = ( ES_AD16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + ad16c4t0_hwtimer.hwtimer_periph = &ad16c4t0_hwtimer_periph; + + ad16c4t0_hwtimer.parent.info = &ad16c4t0_info; + ad16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&ad16c4t0_hwtimer.parent, ES_DEVICE_NAME_AD16C4T0_HWTIMER, &ad16c4t0_hwtimer); +#endif + +#ifdef BSP_USING_AD16C4T1_HWTIMER + static timer_handle_t ad16c4t1_hwtimer_periph; + + ad16c4t1_hwtimer_periph.perh = AD16C4T1; + ad16c4t1_hwtimer.IRQn = AD16C4T1_UP_IRQn; + + ad16c4t1_hwtimer_periph.init.prescaler = ES_AD16C4T1_HWTIMER_PRES - 1; + ad16c4t1_hwtimer_periph.init.mode = ( ES_AD16C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + ad16c4t1_hwtimer.hwtimer_periph = &ad16c4t1_hwtimer_periph; + + ad16c4t1_hwtimer.parent.info = &ad16c4t1_info; + ad16c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&ad16c4t1_hwtimer.parent, ES_DEVICE_NAME_AD16C4T1_HWTIMER, &ad16c4t1_hwtimer); +#endif + +#ifdef BSP_USING_GP32C4T0_HWTIMER + static timer_handle_t gp32c4t0_hwtimer_periph; + + gp32c4t0_hwtimer_periph.perh = GP32C4T0; + gp32c4t0_hwtimer.IRQn = GP32C4T0_IRQn; + + gp32c4t0_hwtimer_periph.init.prescaler = ES_GP32C4T0_HWTIMER_PRES - 1; + gp32c4t0_hwtimer_periph.init.mode = ( ES_GP32C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp32c4t0_hwtimer.hwtimer_periph = &gp32c4t0_hwtimer_periph; + + gp32c4t0_hwtimer.parent.info = &gp32c4t0_info; + gp32c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp32c4t0_hwtimer.parent, ES_DEVICE_NAME_GP32C4T0_HWTIMER, &gp32c4t0_hwtimer); +#endif + +#ifdef BSP_USING_GP32C4T1_HWTIMER + static timer_handle_t gp32c4t1_hwtimer_periph; + + gp32c4t1_hwtimer_periph.perh = GP32C4T1; + gp32c4t1_hwtimer.IRQn = GP32C4T1_IRQn; + + gp32c4t1_hwtimer_periph.init.prescaler = ES_GP32C4T1_HWTIMER_PRES - 1; + gp32c4t1_hwtimer_periph.init.mode = ( ES_GP32C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp32c4t1_hwtimer.hwtimer_periph = &gp32c4t1_hwtimer_periph; + + gp32c4t1_hwtimer.parent.info = &gp32c4t1_info; + gp32c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp32c4t1_hwtimer.parent, ES_DEVICE_NAME_GP32C4T1_HWTIMER, &gp32c4t1_hwtimer); +#endif + +#ifdef BSP_USING_GP16C4T0_HWTIMER + static timer_handle_t gp16c4t0_hwtimer_periph; + + gp16c4t0_hwtimer_periph.perh = GP16C4T0; + gp16c4t0_hwtimer.IRQn = GP16C4T0_IRQn; + + gp16c4t0_hwtimer_periph.init.prescaler = ES_GP16C4T0_HWTIMER_PRES - 1; + gp16c4t0_hwtimer_periph.init.mode = ( ES_GP16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t0_hwtimer.hwtimer_periph = &gp16c4t0_hwtimer_periph; + + gp16c4t0_hwtimer.parent.info = &gp16c4t0_info; + gp16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c4t0_hwtimer.parent, ES_DEVICE_NAME_GP16C4T0_HWTIMER, &gp16c4t0_hwtimer); +#endif + +#ifdef BSP_USING_GP16C4T1_HWTIMER + static timer_handle_t gp16c4t1_hwtimer_periph; + + gp16c4t1_hwtimer_periph.perh = GP16C4T1; + gp16c4t1_hwtimer.IRQn = GP16C4T1_IRQn; + + gp16c4t1_hwtimer_periph.init.prescaler = ES_GP16C4T1_HWTIMER_PRES - 1; + gp16c4t1_hwtimer_periph.init.mode = ( ES_GP16C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t1_hwtimer.hwtimer_periph = &gp16c4t1_hwtimer_periph; + + gp16c4t1_hwtimer.parent.info = &gp16c4t1_info; + gp16c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&gp16c4t1_hwtimer.parent, ES_DEVICE_NAME_GP16C4T1_HWTIMER, &gp16c4t1_hwtimer); +#endif + +#ifdef BSP_USING_BS16T0_HWTIMER + static timer_handle_t bs16t0_hwtimer_periph; + + bs16t0_hwtimer_periph.perh = BS16T0; + bs16t0_hwtimer.IRQn = BS16T0_IRQn; + + bs16t0_hwtimer_periph.init.prescaler = ES_BS16T0_HWTIMER_PRES - 1; + bs16t0_hwtimer_periph.init.mode = ( ES_BS16T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t0_hwtimer.hwtimer_periph = &bs16t0_hwtimer_periph; + + bs16t0_hwtimer.parent.info = &bs16t0_info; + bs16t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t0_hwtimer.parent, ES_DEVICE_NAME_BS16T0_HWTIMER, &bs16t0_hwtimer); +#endif + +#ifdef BSP_USING_BS16T1_HWTIMER + static timer_handle_t bs16t1_hwtimer_periph; + + bs16t1_hwtimer_periph.perh = BS16T1; + bs16t1_hwtimer.IRQn = BS16T1_IRQn; + + bs16t1_hwtimer_periph.init.prescaler = ES_BS16T1_HWTIMER_PRES - 1; + bs16t1_hwtimer_periph.init.mode = ( ES_BS16T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t1_hwtimer.hwtimer_periph = &bs16t1_hwtimer_periph; + + bs16t1_hwtimer.parent.info = &bs16t1_info; + bs16t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; + ret = rt_device_hwtimer_register(&bs16t1_hwtimer.parent, ES_DEVICE_NAME_BS16T1_HWTIMER, &bs16t1_hwtimer); #endif return ret; diff --git a/bsp/essemi/es32f369x/drivers/drv_hwtimer.h b/bsp/essemi/es32f369x/drivers/drv_hwtimer.h index e18d580fbd..46e307a5c3 100644 --- a/bsp/essemi/es32f369x/drivers/drv_hwtimer.h +++ b/bsp/essemi/es32f369x/drivers/drv_hwtimer.h @@ -3,14 +3,28 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-3-19 wangyq the first version + * 2019-3-19 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_HWTIMER_H__ #define DRV_HWTIMER_H__ +#include "es_conf_info_hwtimer.h" int rt_hw_hwtimer_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_i2c.c b/bsp/essemi/es32f369x/drivers/drv_i2c.c index 207890a6d4..2f47915018 100644 --- a/bsp/essemi/es32f369x/drivers/drv_i2c.c +++ b/bsp/essemi/es32f369x/drivers/drv_i2c.c @@ -1,12 +1,24 @@ /* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: - * Date Author Notes - * 2020-01-14 wangyq the first version - * 2019-11-01 wangyq update libraries + * Date Author Notes + * 2019-11-01 wangyq update libraries + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include @@ -14,9 +26,7 @@ #include #include "board.h" #include "drv_i2c.h" -#include -#include -#include + #ifdef RT_USING_I2C @@ -43,36 +53,56 @@ static void _i2c_init(void) gpio_instruct.nodrv = GPIO_OUT_DRIVE_0_1; gpio_instruct.flt = GPIO_FILTER_DISABLE; gpio_instruct.type = GPIO_TYPE_CMOS; - gpio_instruct.func = GPIO_FUNC_5; + #ifdef BSP_USING_I2C0 /* Initialize I2C Function */ - _h_i2c0.perh = I2C0; - _h_i2c0.init.clk_speed = 100000; - _h_i2c0.init.own_addr1 = 0x0A; - _h_i2c0.init.addr_mode = I2C_ADDR_7BIT; - _h_i2c0.init.general_call = I2C_GENERALCALL_DISABLE; - _h_i2c0.init.no_stretch = I2C_NOSTRETCH_ENABLE; + _h_i2c0.perh = I2C0; + _h_i2c0.init.module = I2C_MODULE_MASTER; + _h_i2c0.init.clk_speed = ES_I2C0_CLK_SPEED; + _h_i2c0.init.own_addr1 = ES_I2C0_OWN_ADDR1; + _h_i2c0.init.addr_mode = ES_I2C0_ADDR_MODE; + _h_i2c0.init.general_call = ES_I2C0_GENERAL_CALL; + _h_i2c0.init.no_stretch = ES_I2C0_STRETCH; ald_i2c_reset(&_h_i2c0); ald_i2c_init(&_h_i2c0); - /* PB06->I2C0_SCL, PB07->I2C0_SDA */ - ald_gpio_init(GPIOB, GPIO_PIN_6 | GPIO_PIN_7, &gpio_instruct); + +#if defined(ES_I2C0_SCL_GPIO_FUNC)&&defined(ES_I2C0_SCL_GPIO_PORT)&&defined(ES_I2C0_SCL_GPIO_PIN) + gpio_instruct.func = ES_I2C0_SCL_GPIO_FUNC; + ald_gpio_init(ES_I2C0_SCL_GPIO_PORT, ES_I2C0_SCL_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_I2C0_SDA_GPIO_FUNC)&&defined(ES_I2C0_SDA_GPIO_PORT)&&defined(ES_I2C0_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C0_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C0_SDA_GPIO_PORT, ES_I2C0_SDA_GPIO_PIN, &gpio_instruct); +#endif + #endif #ifdef BSP_USING_I2C1 /* Initialize i2c function */ - _h_i2c1.perh = I2C1; - _h_i2c1.init.clk_speed = 100000; - _h_i2c1.init.own_addr1 = 0xA0; - _h_i2c1.init.addr_mode = I2C_ADDR_7BIT; - _h_i2c1.init.general_call = I2C_GENERALCALL_DISABLE; - _h_i2c1.init.no_stretch = I2C_NOSTRETCH_ENABLE; + _h_i2c1.perh = I2C1; + _h_i2c1.init.module = I2C_MODULE_MASTER; + _h_i2c1.init.clk_speed = ES_I2C1_CLK_SPEED; + _h_i2c1.init.own_addr1 = ES_I2C1_OWN_ADDR1; + _h_i2c1.init.addr_mode = ES_I2C1_ADDR_MODE; + _h_i2c1.init.general_call = ES_I2C1_GENERAL_CALL; + _h_i2c1.init.no_stretch = ES_I2C1_STRETCH; ald_i2c_reset(&_h_i2c1); ald_i2c_init(&_h_i2c1); - /* PA05->I2C1_SCL, PA06->I2C1_SDA */ - ald_gpio_init(GPIOA, GPIO_PIN_5 | GPIO_PIN_6, &gpio_instruct); + +#if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) + gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC; + ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct); +#endif + #endif } @@ -133,7 +163,7 @@ int rt_hw_i2c_init(void) _i2c_device0.ops = &es32f3_i2c_ops; _i2c_device0.priv = &_h_i2c0; - result = rt_i2c_bus_device_register(&_i2c_device0, "i2c0"); + result = rt_i2c_bus_device_register(&_i2c_device0, ES_DEVICE_NAME_I2C0); if (result != RT_EOK) { return result; @@ -147,7 +177,7 @@ int rt_hw_i2c_init(void) _i2c_device1.ops = &es32f3_i2c_ops; _i2c_device1.priv = &_h_i2c1; - rt_i2c_bus_device_register(&_i2c_device1, "i2c1"); + rt_i2c_bus_device_register(&_i2c_device1, ES_DEVICE_NAME_I2C1); if (result != RT_EOK) { return result; diff --git a/bsp/essemi/es32f369x/drivers/drv_i2c.h b/bsp/essemi/es32f369x/drivers/drv_i2c.h index d7c2410682..16bfa324d3 100644 --- a/bsp/essemi/es32f369x/drivers/drv_i2c.h +++ b/bsp/essemi/es32f369x/drivers/drv_i2c.h @@ -1,16 +1,31 @@ /* * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_I2C_H__ #define DRV_I2C_H__ +#include "es_conf_info_i2c.h" + int rt_hw_i2c_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_pm.c b/bsp/essemi/es32f369x/drivers/drv_pm.c index ffe46ff6f3..5ec1c8c701 100644 --- a/bsp/essemi/es32f369x/drivers/drv_pm.c +++ b/bsp/essemi/es32f369x/drivers/drv_pm.c @@ -3,16 +3,27 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2020-12-15 liuhy the first version */ -#include "drv_pm.h" +#include "drv_pm.h" #ifdef RT_USING_PM -//uint32_t save_mem[1024] __attribute__ ((aligned(4))); void save_register(void *p_head,uint32_t size,void *p_save) { @@ -21,15 +32,17 @@ void save_register(void *p_head,uint32_t size,void *p_save) void load_register(void *p_head,uint32_t size,void *p_load) { - uint32_t tmp; memcpy(p_head,p_load,size); - + +#ifdef ES_PMU_SAVE_LOAD_UART + if((p_head == UART0) || (p_head == UART1) || (p_head == UART2) || (p_head == UART3) || (p_head == UART4) || (p_head == UART5) ) { - tmp = ((UART_TypeDef*)p_load)->IVS; - ((UART_TypeDef*)p_head)->IER = tmp; + ((UART_TypeDef*)p_head)->IER = ((UART_TypeDef*)p_load)->IVS; } +#endif + } static void uart_console_reconfig(void) @@ -39,36 +52,14 @@ static void uart_console_reconfig(void) rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config); } -static void delay(void) -{ - long i; - rt_base_t level; - - level = rt_hw_interrupt_disable(); - i = 0; - do{ - i++; - } - while (i < 4000000); - - rt_hw_interrupt_enable(level); -} - /** * This function will put ES32F369x into sleep mode. * * @param pm pointer to power manage structure */ -struct pm_callback_t -{ - volatile int in_fun_times; /*进入函数的次数*/ - volatile char flag; /*标志*/ - volatile int mode; /*需要打印的模式*/ -}; - -extern volatile struct pm_callback_t g_pm_data; +/* 注意：进入睡眠前，如果有中断挂起（SYSTICK、PENDSV、UART、EXTI等），睡眠将被瞬间唤醒。*/ static void sleep(struct rt_pm *pm, uint8_t mode) { @@ -83,26 +74,21 @@ static void sleep(struct rt_pm *pm, uint8_t mode) case PM_SLEEP_MODE_LIGHT: /* Enter SLEEP Mode, Main regulator is ON */ ald_pmu_stop1_enter(); - delay(); - break; case PM_SLEEP_MODE_DEEP: - /* Enter STOP 2 mode */ + /* Enter STOP 2 mode */ ald_pmu_stop2_enter(); - delay(); break; case PM_SLEEP_MODE_STANDBY: - /* Enter STANDBY mode */ + /* Enter STANDBY mode */ ald_pmu_stop2_enter(); - delay(); break; case PM_SLEEP_MODE_SHUTDOWN: - /* Enter SHUTDOWNN mode */ + /* Enter SHUTDOWNN mode */ ald_pmu_stop2_enter(); - delay(); break; default: diff --git a/bsp/essemi/es32f369x/drivers/drv_pm.h b/bsp/essemi/es32f369x/drivers/drv_pm.h index 56de29eef5..874f86ed08 100644 --- a/bsp/essemi/es32f369x/drivers/drv_pm.h +++ b/bsp/essemi/es32f369x/drivers/drv_pm.h @@ -3,9 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-04-01 wangyq the first version + * 2019-04-01 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_PM_H__ @@ -14,9 +27,8 @@ #include #include #include -#include -#include -#include "shell.h" +#include "es_conf_info_pm.h" +#include int rt_hw_pm_init(void); diff --git a/bsp/essemi/es32f369x/drivers/drv_pwm.c b/bsp/essemi/es32f369x/drivers/drv_pwm.c index e033e47cec..b61e363633 100644 --- a/bsp/essemi/es32f369x/drivers/drv_pwm.c +++ b/bsp/essemi/es32f369x/drivers/drv_pwm.c @@ -3,28 +3,33 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-03-11 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include #include #include -#include -#include -#include +#include "es_conf_info_pwm.h" -static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns) -{ - uint64_t _arr = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 / - (timer_initstruct->init.prescaler + 1); - WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr); - timer_initstruct->init.period = (uint32_t)_arr; -} +#ifdef RT_USING_PWM static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, uint32_t ns) { @@ -44,37 +49,40 @@ static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, u static rt_err_t es32f3_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) { rt_err_t ret = RT_EOK; - uint32_t _ccep; + uint64_t _arr,bus_speed,tmp; + uint32_t _maxcnt,_ccep_ch_en = 0U; timer_channel_t pwm_channel; timer_oc_init_t tim_ocinit; timer_handle_t *timer_initstruct = (timer_handle_t *)device->parent.user_data; struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg; RT_ASSERT(timer_initstruct != RT_NULL); - - tim_ocinit.oc_mode = TIMER_OC_MODE_PWM1; - tim_ocinit.oc_polarity = TIMER_OC_POLARITY_HIGH; - tim_ocinit.oc_fast_en = DISABLE; - tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH; - tim_ocinit.ocn_idle = TIMER_OCN_IDLE_RESET; - tim_ocinit.oc_idle = TIMER_OC_IDLE_RESET; - + + /* select pwm output channel */ if (1 == cfg->channel) + { pwm_channel = TIMER_CHANNEL_1; - - else if (2 == cfg->channel) + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC1EN_MSK; + } + else if (2 == cfg->channel) + { pwm_channel = TIMER_CHANNEL_2; - - else if (3 == cfg->channel) + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC2EN_MSK; + } + else if (3 == cfg->channel) + { pwm_channel = TIMER_CHANNEL_3; - - else if (4 == cfg->channel) + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC3EN_MSK; + } + else if (4 == cfg->channel) + { pwm_channel = TIMER_CHANNEL_4; - + _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC4EN_MSK; + } else return RT_EINVAL; - + switch (cmd) { case PWM_CMD_ENABLE: @@ -86,19 +94,53 @@ static rt_err_t es32f3_pwm_control(struct rt_device_pwm *device, int cmd, void * break; case PWM_CMD_SET: - _ccep = timer_initstruct->perh->CCEP; - /* count registers max 0xFFFF, auto adjust prescaler */ + + /*当通道没开的时候：关通道，设置输出模式和极性，初始化通道*/ + if(!_ccep_ch_en) + { + tim_ocinit.oc_mode = ES_PWM_OC_MODE; + tim_ocinit.oc_polarity = ES_PWM_OC_POLARITY; + tim_ocinit.oc_fast_en = DISABLE; + tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH; + tim_ocinit.ocn_idle = TIMER_OCN_IDLE_RESET; + tim_ocinit.oc_idle = TIMER_OC_IDLE_RESET; + + ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); + } + + bus_speed = (uint64_t)ald_cmu_get_pclk1_clock(); + + /*判断外设的计数器最大值*/ +#ifdef ES32F36xx + if((timer_initstruct->perh == GP32C4T0)||(timer_initstruct->perh == GP32C4T1)) + { + _maxcnt = 0xFFFFFFFF; + } + else _maxcnt = 0xFFFF; +#else + _maxcnt = 0xFFFF; +#endif + + /*当最大分频 <= _maxcnt时：估计大概的分频，加快速度 */ + tmp = bus_speed * (cfg->period)/1000000000/_maxcnt; + timer_initstruct->init.prescaler = (tmp > 2U) ? (tmp - 2U) : 0U ; /*bus_speed < 500000000*/ + + /* count registers max , auto adjust prescaler */ do { - pwm_set_freq(timer_initstruct, cfg->period); - timer_initstruct->init.prescaler ++; + _arr = bus_speed * (cfg->period) / 1000000000 /(++timer_initstruct->init.prescaler); + } - while (timer_initstruct->init.period > 0xFFFF); + while (_arr > _maxcnt); + + WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr); + timer_initstruct->init.period = (uint32_t)_arr; + /* update prescaler */ WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler); - ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); + pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse); - timer_initstruct->perh->CCEP = _ccep; + break; case PWM_CMD_GET: @@ -130,42 +172,210 @@ int rt_hw_pwm_init(void) gpio_initstructure.flt = GPIO_FILTER_DISABLE; gpio_initstructure.type = GPIO_TYPE_TTL; -#ifdef BSP_USING_PWM0 /* 4 channels */ - static struct rt_device_pwm pwm_dev0; - static timer_handle_t timer_initstruct0; +#ifdef BSP_USING_AD16C4T0_PWM /* 4 channels */ + static struct rt_device_pwm ad16c4t0_pwm_dev; + static timer_handle_t ad16c4t0_timer_initstruct; + + ad16c4t0_timer_initstruct.perh = AD16C4T0; + ald_timer_pwm_init(&ad16c4t0_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_AD16C4T0_CH1_GPIO_FUNC)&&defined(ES_AD16C4T0_CH1_GPIO_PORT)&&defined(ES_AD16C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH1_GPIO_PORT, ES_AD16C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH2_GPIO_FUNC)&&defined(ES_AD16C4T0_CH2_GPIO_PORT)&&defined(ES_AD16C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH2_GPIO_PORT, ES_AD16C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH3_GPIO_FUNC)&&defined(ES_AD16C4T0_CH3_GPIO_PORT)&&defined(ES_AD16C4T0_CH3_GPIO_FUNC) + gpio_initstructure.func = ES_AD16C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH3_GPIO_PORT, ES_AD16C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T0_CH4_GPIO_FUNC)&&defined(ES_AD16C4T0_CH4_GPIO_PORT)&&defined(ES_AD16C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T0_CH4_GPIO_PORT, ES_AD16C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&ad16c4t0_pwm_dev, ES_DEVICE_NAME_AD16C4T0_PWM, &es32f3_pwm_ops, + &ad16c4t0_timer_initstruct); +#endif + +#ifdef BSP_USING_AD16C4T1_PWM /* 4 channels */ + static struct rt_device_pwm ad16c4t1_pwm_dev; + static timer_handle_t ad16c4t1_timer_initstruct; + + ad16c4t1_timer_initstruct.perh = AD16C4T1; + ald_timer_pwm_init(&ad16c4t1_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_AD16C4T1_CH1_GPIO_FUNC)&&defined(ES_AD16C4T1_CH1_GPIO_PORT)&&defined(ES_AD16C4T1_CH1_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH1_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH1_GPIO_PORT, ES_AD16C4T1_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T1_CH2_GPIO_FUNC)&&defined(ES_AD16C4T1_CH2_GPIO_PORT)&&defined(ES_AD16C4T1_CH2_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH2_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH2_GPIO_PORT, ES_AD16C4T1_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T1_CH3_GPIO_FUNC)&&defined(ES_AD16C4T1_CH3_GPIO_PORT)&&defined(ES_AD16C4T1_CH3_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH3_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH3_GPIO_PORT, ES_AD16C4T1_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_AD16C4T1_CH4_GPIO_FUNC)&&defined(ES_AD16C4T1_CH4_GPIO_PORT)&&defined(ES_AD16C4T1_CH4_GPIO_PIN) + gpio_initstructure.func = ES_AD16C4T1_CH4_GPIO_FUNC; + ald_gpio_init(ES_AD16C4T1_CH4_GPIO_PORT, ES_AD16C4T1_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&ad16c4t1_pwm_dev, ES_DEVICE_NAME_AD16C4T1_PWM, &es32f3_pwm_ops, + &ad16c4t1_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP32C4T0_PWM /* 4 channels */ + static struct rt_device_pwm gp32c4t0_pwm_dev; + static timer_handle_t gp32c4t0_timer_initstruct; + + gp32c4t0_timer_initstruct.perh = GP32C4T0; + ald_timer_pwm_init(&gp32c4t0_timer_initstruct); + + /* gpio initialization */ + +#if defined(ES_GP32C4T0_CH1_GPIO_FUNC)&&defined(ES_GP32C4T0_CH1_GPIO_PORT)&&defined(ES_GP32C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH1_GPIO_PORT, ES_GP32C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T0_CH2_GPIO_FUNC)&&defined(ES_GP32C4T0_CH2_GPIO_PORT)&&defined(ES_GP32C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH2_GPIO_PORT, ES_GP32C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T0_CH3_GPIO_FUNC)&&defined(ES_GP32C4T0_CH3_GPIO_PORT)&&defined(ES_GP32C4T0_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH3_GPIO_PORT, ES_GP32C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T0_CH4_GPIO_FUNC)&&defined(ES_GP32C4T0_CH4_GPIO_PORT)&&defined(ES_GP32C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T0_CH4_GPIO_PORT, ES_GP32C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp32c4t0_pwm_dev, ES_DEVICE_NAME_AD16C4T1_PWM, &es32f3_pwm_ops, + &gp32c4t0_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP32C4T1_PWM /* 4 channels */ + static struct rt_device_pwm gp32c4t1_pwm_dev; + static timer_handle_t gp32c4t1_timer_initstruct; + + gp32c4t1_timer_initstruct.perh = GP32C4T1; + ald_timer_pwm_init(&gp32c4t1_timer_initstruct); - timer_initstruct0.perh = GP16C4T0; - ald_timer_pwm_init(&timer_initstruct0); + /* gpio initialization */ + +#if defined(ES_GP32C4T1_CH1_GPIO_FUNC)&&defined(ES_GP32C4T1_CH1_GPIO_PORT)&&defined(ES_GP32C4T1_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH1_GPIO_PORT, ES_GP32C4T1_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T1_CH2_GPIO_FUNC)&&defined(ES_GP32C4T1_CH2_GPIO_PORT)&&defined(ES_GP32C4T1_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH2_GPIO_PORT, ES_GP32C4T1_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T1_CH3_GPIO_FUNC)&&defined(ES_GP32C4T1_CH3_GPIO_PORT)&&defined(ES_GP32C4T1_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH3_GPIO_PORT, ES_GP32C4T1_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP32C4T1_CH4_GPIO_FUNC)&&defined(ES_GP32C4T1_CH4_GPIO_PORT)&&defined(ES_GP32C4T1_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP32C4T1_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP32C4T1_CH4_GPIO_PORT, ES_GP32C4T1_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp32c4t1_pwm_dev, ES_DEVICE_NAME_GP32C4T1_PWM, &es32f3_pwm_ops, + &gp32c4t1_timer_initstruct); +#endif + + +#ifdef BSP_USING_GP16C4T0_PWM /* 4 channels */ + static struct rt_device_pwm gp16c4t0_pwm_dev; + static timer_handle_t gp16c4t0_timer_initstruct; + + gp16c4t0_timer_initstruct.perh = GP16C4T0; + ald_timer_pwm_init(&gp16c4t0_timer_initstruct); /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_2; - ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure); - - ret = rt_device_pwm_register(&pwm_dev0, "pwm0", &es32f3_pwm_ops, - &timer_initstruct0); + +#if defined(ES_GP16C4T0_CH1_GPIO_FUNC)&&defined(ES_GP16C4T0_CH1_GPIO_PORT)&&defined(ES_GP16C4T0_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH1_GPIO_PORT, ES_GP16C4T0_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH2_GPIO_FUNC)&&defined(ES_GP16C4T0_CH2_GPIO_PORT)&&defined(ES_GP16C4T0_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH2_GPIO_PORT, ES_GP16C4T0_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH3_GPIO_FUNC)&&defined(ES_GP16C4T0_CH3_GPIO_PORT)&&defined(ES_GP16C4T0_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH3_GPIO_PORT, ES_GP16C4T0_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T0_CH4_GPIO_FUNC)&&defined(ES_GP16C4T0_CH4_GPIO_PORT)&&defined(ES_GP16C4T0_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T0_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T0_CH4_GPIO_PORT, ES_GP16C4T0_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp16c4t0_pwm_dev, ES_DEVICE_NAME_GP16C4T0_PWM, &es32f3_pwm_ops, + &gp16c4t0_timer_initstruct); #endif -#ifdef BSP_USING_PWM1 /* 4 channels */ - static struct rt_device_pwm pwm_dev1; - static timer_handle_t timer_initstruct1; - timer_initstruct1.perh = GP16C4T1; - ald_timer_pwm_init(&timer_initstruct1); +#ifdef BSP_USING_GP16C4T1_PWM /* 4 channels */ + static struct rt_device_pwm gp16c4t1_pwm_dev; + static timer_handle_t gp16c4t1_timer_initstruct; + + gp16c4t1_timer_initstruct.perh = GP16C4T1; + ald_timer_pwm_init(&gp16c4t1_timer_initstruct); /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_5; - ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstructure); - - ret = rt_device_pwm_register(&pwm_dev1, "pwm1", &es32f3_pwm_ops, - &timer_initstruct1); + +#if defined(ES_GP16C4T1_CH1_GPIO_FUNC)&&defined(ES_GP16C4T1_CH1_GPIO_PORT)&&defined(ES_GP16C4T1_CH1_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH1_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH1_GPIO_PORT, ES_GP16C4T1_CH1_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T1_CH2_GPIO_FUNC)&&defined(ES_GP16C4T1_CH2_GPIO_PORT)&&defined(ES_GP16C4T1_CH2_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH2_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH2_GPIO_PORT, ES_GP16C4T1_CH2_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T1_CH3_GPIO_FUNC)&&defined(ES_GP16C4T1_CH3_GPIO_PORT)&&defined(ES_GP16C4T1_CH3_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH3_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH3_GPIO_PORT, ES_GP16C4T1_CH3_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_GP16C4T1_CH4_GPIO_FUNC)&&defined(ES_GP16C4T1_CH4_GPIO_PORT)&&defined(ES_GP16C4T1_CH4_GPIO_PIN) + gpio_initstructure.func = ES_GP16C4T1_CH4_GPIO_FUNC; + ald_gpio_init(ES_GP16C4T1_CH4_GPIO_PORT, ES_GP16C4T1_CH4_GPIO_PIN, &gpio_initstructure); +#endif + + ret = rt_device_pwm_register(&gp16c4t1_pwm_dev, ES_DEVICE_NAME_GP16C4T1_PWM, &es32f3_pwm_ops, + &gp16c4t1_timer_initstruct); #endif return ret; } INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_rtc.c b/bsp/essemi/es32f369x/drivers/drv_rtc.c index cab5b8b61b..13b0fc9a24 100644 --- a/bsp/essemi/es32f369x/drivers/drv_rtc.c +++ b/bsp/essemi/es32f369x/drivers/drv_rtc.c @@ -3,21 +3,32 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2019-03-22 wangyq the first version - * 2019-11-01 wangyq update libraries + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version */ #include #include -#include +#include #include #include #include "board.h" -#include "drv_rtc.h" -#include -#include +#include "drv_rtc.h" #ifdef RT_USING_RTC @@ -117,20 +128,28 @@ int rt_hw_rtc_init(void) rt_err_t ret = RT_EOK; static struct rt_device rtc_dev; rtc_init_t rtc_initstruct; + + /* enable clk */ + ald_rtc_source_select(ES_RTC_CLK_SOURCE); - /* enable external 32.768kHz */ - CMU_LOSC_ENABLE(); - ald_cmu_losc_safe_config(ENABLE); + if(ES_RTC_CLK_SOURCE == ES_C_RTC_SOURCE_LOSC) + { + CMU_LOSC_ENABLE(); + ald_cmu_losc_safe_config(ENABLE); + } + /* set default time */ RTC_UNLOCK(); WRITE_REG(RTC->TIME, 0x134251); WRITE_REG(RTC->DATE, 0x1190401); RTC_LOCK(); + /* RTC function initialization */ rtc_initstruct.hour_format = RTC_HOUR_FORMAT_24; rtc_initstruct.asynch_pre_div = 0; rtc_initstruct.synch_pre_div = 32767; - rtc_initstruct.output = RTC_OUTPUT_DISABLE; + rtc_initstruct.output = RTC_OUTPUT_DISABLE; + rtc_initstruct.output_polarity = RTC_OUTPUT_POLARITY_HIGH; __rtc_init(&rtc_initstruct); rtc_dev.type = RT_Device_Class_RTC; @@ -150,7 +169,7 @@ int rt_hw_rtc_init(void) rtc_dev.user_data = RTC; - ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR); + ret = rt_device_register(&rtc_dev, ES_DEVICE_NAME_RTC, RT_DEVICE_FLAG_RDWR); return ret; } diff --git a/bsp/essemi/es32f369x/drivers/drv_rtc.h b/bsp/essemi/es32f369x/drivers/drv_rtc.h index fe0264fb51..76e5b24d85 100644 --- a/bsp/essemi/es32f369x/drivers/drv_rtc.h +++ b/bsp/essemi/es32f369x/drivers/drv_rtc.h @@ -3,14 +3,28 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2019-03-22 wangyq the first version + * 2019-03-22 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_RTC_H__ #define DRV_RTC_H__ +#include "es_conf_info_rtc.h" int rt_hw_rtc_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/drv_spi.c b/bsp/essemi/es32f369x/drivers/drv_spi.c index 9bf7e4e4b5..aae178f78e 100644 --- a/bsp/essemi/es32f369x/drivers/drv_spi.c +++ b/bsp/essemi/es32f369x/drivers/drv_spi.c @@ -3,10 +3,23 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: - * Date Author Notes - * 2020-01-14 wangyq the first version - * 2019-11-01 wangyq update libraries + * Date Author Notes + * 2019-11-01 wangyq update libraries + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include @@ -15,9 +28,7 @@ #include #include "board.h" #include "drv_spi.h" -#include -#include -#include + #ifdef RT_USING_SPI @@ -31,6 +42,7 @@ rt_err_t spi_configure(struct rt_spi_device *device, hspi->init.ss_en = DISABLE; hspi->init.crc_calc = DISABLE; + hspi->init.frame = SPI_FRAME_MOTOROLA; /* config spi mode */ if (cfg->mode & RT_SPI_SLAVE) @@ -163,73 +175,54 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * hspi = (spi_handle_t *)device->bus->parent.user_data; cs = device->parent.user_data; + if (message->cs_take) + { + rt_pin_write(cs->pin, ES_SPI_CS_LEVEL); + } + if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL) { /* send & receive */ if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL)) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } else { /* only send data */ if (message->recv_buf == RT_NULL) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } /* only receive data */ if (message->send_buf == RT_NULL) { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; } } - + + if (message->cs_release) + { + rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL); + } + + if (res != RT_EOK) + return RT_ERROR; + else + return message->length; + } else { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } - + if (message->cs_release) { - rt_pin_write(cs->pin, 1); + rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL); } return RT_EOK; } - return message->length; + } const struct rt_spi_ops es32f3_spi_ops = @@ -240,6 +233,7 @@ const struct rt_spi_ops es32f3_spi_ops = rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name) { + int result; /* define spi Instance */ struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); RT_ASSERT(spi_device != RT_NULL); @@ -248,7 +242,20 @@ rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const c cs_pin->pin = pin; rt_pin_mode(pin, PIN_MODE_OUTPUT); rt_pin_write(pin, 1); - return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + +#ifdef BSP_USING_SPI0 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI0_BUS)))SPI_BUS_CONFIG(spi_device->config,0); +#endif +#ifdef BSP_USING_SPI1 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI1_BUS)))SPI_BUS_CONFIG(spi_device->config,1); +#endif +#ifdef BSP_USING_SPI2 + if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI2_BUS)))SPI_BUS_CONFIG(spi_device->config,2); +#endif + + return result; } #ifdef BSP_USING_SPI0 @@ -273,40 +280,47 @@ int rt_hw_spi_init(void) struct rt_spi_bus *spi_bus; spi_handle_t *spi; gpio_init_t gpio_instruct; - + + gpio_instruct.pupd = GPIO_PUSH_UP_DOWN; + gpio_instruct.odos = GPIO_PUSH_PULL; + gpio_instruct.podrv = GPIO_OUT_DRIVE_1; + gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; + gpio_instruct.type = GPIO_TYPE_TTL; + gpio_instruct.flt = GPIO_FILTER_DISABLE; + #ifdef BSP_USING_SPI0 _spi0.perh = SPI0; spi_bus = &_spi_bus0; spi = &_spi0; - rt_device_t spi_bus_dev0; /* SPI0 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.podrv = GPIO_OUT_DRIVE_1; - gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; - gpio_instruct.func = GPIO_FUNC_4; - gpio_instruct.type = GPIO_TYPE_TTL; - gpio_instruct.flt = GPIO_FILTER_DISABLE; - /* PB3->SPI0_SCK, PB5->SPI0_MOSI */ - ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct); +#if defined(ES_SPI0_SCK_GPIO_FUNC)&&defined(ES_SPI0_SCK_GPIO_PORT)&&defined(ES_SPI0_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI0_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI0_SCK_GPIO_PORT, ES_SPI0_SCK_GPIO_PIN, &gpio_instruct); +#endif - /* PB4->SPI0_MISO */ +#if defined(ES_SPI0_MOSI_GPIO_FUNC)&&defined(ES_SPI0_MOSI_GPIO_PORT)&&defined(ES_SPI0_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI0_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI0_MOSI_GPIO_PORT, ES_SPI0_MOSI_GPIO_PIN, &gpio_instruct); +#endif + gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct); + +#if defined(ES_SPI0_MISO_GPIO_FUNC)&&defined(ES_SPI0_MISO_GPIO_PORT)&&defined(ES_SPI0_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI0_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI0_MISO_GPIO_PORT, ES_SPI0_MISO_GPIO_PIN, &gpio_instruct); +#endif spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi0", &es32f3_spi_ops); + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI0_BUS, &es32f3_spi_ops); if (result != RT_EOK) { return result; } - rt_device_register(spi_bus_dev0, "spi00", RT_DEVICE_FLAG_RDWR); - - /* SPI0_NSS = PA15 = PIN 50 */ - result = es32f3_spi_device_attach(50, "spi0", "spi00"); + result = es32f3_spi_device_attach(ES_SPI0_NSS_PIN, ES_DEVICE_NAME_SPI0_BUS, ES_DEVICE_NAME_SPI0_DEV0); if (result != RT_EOK) { @@ -319,35 +333,35 @@ int rt_hw_spi_init(void) _spi1.perh = SPI1; spi_bus = &_spi_bus1; spi = &_spi1; - rt_device_t spi_bus_dev0; /* SPI1 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.podrv = GPIO_OUT_DRIVE_1; - gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; - gpio_instruct.func = GPIO_FUNC_4; - gpio_instruct.type = GPIO_TYPE_TTL; - gpio_instruct.flt = GPIO_FILTER_DISABLE; - - /* PC01->SPI1_SCK, PC03->SPI1_MOSI */ - ald_gpio_init(GPIOC, GPIO_PIN_1 | GPIO_PIN_3, &gpio_instruct); - - /* PC02->SPI1_MISO */ + +#if defined(ES_SPI1_SCK_GPIO_FUNC)&&defined(ES_SPI1_SCK_GPIO_PORT)&&defined(ES_SPI1_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI1_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI1_SCK_GPIO_PORT, ES_SPI1_SCK_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_SPI1_MOSI_GPIO_FUNC)&&defined(ES_SPI1_MOSI_GPIO_PORT)&&defined(ES_SPI1_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI1_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI1_MOSI_GPIO_PORT, ES_SPI1_MOSI_GPIO_PIN, &gpio_instruct); +#endif + gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_instruct); + +#if defined(ES_SPI1_MISO_GPIO_FUNC)&&defined(ES_SPI1_MISO_GPIO_PORT)&&defined(ES_SPI1_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI1_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI1_MISO_GPIO_PORT, ES_SPI1_MISO_GPIO_PIN, &gpio_instruct); +#endif spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi1", &es32f3_spi_ops); + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI1_BUS, &es32f3_spi_ops); if (result != RT_EOK) { return result; } - rt_device_register(spi_bus_dev0, "spi10", RT_DEVICE_FLAG_RDWR); - - /* SPI1_NSS = PC00 = PIN 8 */ - result = es32f3_spi_device_attach(8, "spi1", "spi10"); + result = es32f3_spi_device_attach(ES_SPI1_NSS_PIN, ES_DEVICE_NAME_SPI1_BUS, ES_DEVICE_NAME_SPI1_DEV0); if (result != RT_EOK) { @@ -357,38 +371,38 @@ int rt_hw_spi_init(void) #endif #ifdef BSP_USING_SPI2 - _spi1.perh = SPI2; + _spi2.perh = SPI2; spi_bus = &_spi_bus2; spi = &_spi2; - rt_device_t spi_bus_dev0; /* SPI2 gpio init */ gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.podrv = GPIO_OUT_DRIVE_1; - gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; - gpio_instruct.func = GPIO_FUNC_5; - gpio_instruct.type = GPIO_TYPE_TTL; - gpio_instruct.flt = GPIO_FILTER_DISABLE; - - /* PC05->SPI1_SCK, PB01->SPI1_MOSI */ - ald_gpio_init(GPIOC, GPIO_PIN_5 | GPIO_PIN_1, &gpio_instruct); - - /* PB00->SPI1_MISO */ + +#if defined(ES_SPI2_SCK_GPIO_FUNC)&&defined(ES_SPI2_SCK_GPIO_PORT)&&defined(ES_SPI2_SCK_GPIO_PIN) + gpio_instruct.func = ES_SPI2_SCK_GPIO_FUNC; + ald_gpio_init(ES_SPI2_SCK_GPIO_PORT, ES_SPI2_SCK_GPIO_PIN, &gpio_instruct); +#endif + +#if defined(ES_SPI2_MOSI_GPIO_FUNC)&&defined(ES_SPI2_MOSI_GPIO_PORT)&&defined(ES_SPI2_MOSI_GPIO_PIN) + gpio_instruct.func = ES_SPI2_MOSI_GPIO_FUNC; + ald_gpio_init(ES_SPI2_MOSI_GPIO_PORT, ES_SPI2_MOSI_GPIO_PIN, &gpio_instruct); +#endif + gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_instruct); + +#if defined(ES_SPI2_MISO_GPIO_FUNC)&&defined(ES_SPI2_MISO_GPIO_PORT)&&defined(ES_SPI2_MISO_GPIO_PIN) + gpio_instruct.func = ES_SPI2_MISO_GPIO_FUNC; + ald_gpio_init(ES_SPI2_MISO_GPIO_PORT, ES_SPI2_MISO_GPIO_PIN, &gpio_instruct); +#endif spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi2", &es32f3_spi_ops); + result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI2_BUS, &es32f3_spi_ops); if (result != RT_EOK) { return result; } - rt_device_register(spi_bus_dev0, "spi20", RT_DEVICE_FLAG_RDWR); - - /* SPI2_NSS = PC04 = PIN 24 */ - result = es32f3_spi_device_attach(39, "spi2", "spi20"); + result = es32f3_spi_device_attach(ES_SPI2_NSS_PIN, ES_DEVICE_NAME_SPI2_BUS, ES_DEVICE_NAME_SPI1_DEV0); if (result != RT_EOK) { diff --git a/bsp/essemi/es32f369x/drivers/drv_spi.h b/bsp/essemi/es32f369x/drivers/drv_spi.h index 832d1a58b1..32eab04cc5 100644 --- a/bsp/essemi/es32f369x/drivers/drv_spi.h +++ b/bsp/essemi/es32f369x/drivers/drv_spi.h @@ -3,9 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #ifndef DRV_SPI_H__ @@ -14,6 +27,8 @@ #include #include #include + +#include "es_conf_info_spi.h" struct es32f3_hw_spi_cs { diff --git a/bsp/essemi/es32f369x/drivers/drv_uart.c b/bsp/essemi/es32f369x/drivers/drv_uart.c index b6a8b7a453..5ca5085c54 100644 --- a/bsp/essemi/es32f369x/drivers/drv_uart.c +++ b/bsp/essemi/es32f369x/drivers/drv_uart.c @@ -3,19 +3,29 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes - * 2020-01-14 wangyq the first version + * 2020-01-14 wangyq the first version + * 2021-04-20 liuhy the second version */ #include #include #include #include "board.h" -#include "drv_uart.h" -#include -#include -#include +#include "es_conf_info_uart.h" #ifdef RT_USING_SERIAL @@ -26,183 +36,6 @@ struct es32_uart IRQn_Type irq; }; -static rt_err_t es32f3x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - gpio_init_t gpio_initstructure; - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - /* Initialize tx pin */ - gpio_initstructure.mode = GPIO_MODE_OUTPUT; - gpio_initstructure.odos = GPIO_PUSH_PULL; - gpio_initstructure.pupd = GPIO_PUSH_UP; - gpio_initstructure.podrv = GPIO_OUT_DRIVE_1; - gpio_initstructure.nodrv = GPIO_OUT_DRIVE_1; - gpio_initstructure.flt = GPIO_FILTER_DISABLE; - gpio_initstructure.type = GPIO_TYPE_TTL; - -#ifdef BSP_USING_UART0 - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART0, ENABLE); -#endif /* uart0 gpio init */ - -#ifdef BSP_USING_UART1 - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART1, ENABLE); -#endif /* uart1 gpio init */ - -#ifdef BSP_USING_UART2 - gpio_initstructure.func = GPIO_FUNC_5; - ald_gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART2, ENABLE); -#endif /* uart2 gpio init */ - -#ifdef BSP_USING_UART3 - gpio_initstructure.func = GPIO_FUNC_4; - ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART3, ENABLE); -#endif /* uart3 gpio init */ - -#ifdef BSP_USING_UART4 - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART4, ENABLE); -#endif /* uart4 gpio init */ - -#ifdef BSP_USING_UART5 - gpio_initstructure.func = GPIO_FUNC_4; - ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure); - - ald_cmu_perh_clock_config(CMU_PERH_UART5, ENABLE); -#endif /* uart5 gpio init */ - - ald_uart_tx_fifo_config(&uart->huart, UART_TXFIFO_EMPTY); - ald_uart_rx_fifo_config(&uart->huart, UART_RXFIFO_1BYTE); - - uart->huart.init.mode = UART_MODE_UART; - uart->huart.init.baud = cfg->baud_rate; - uart->huart.init.word_length = (uart_word_length_t)(8 - cfg->data_bits); - uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); - uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; - ald_uart_init(&uart->huart); - - if (cfg->bit_order == BIT_ORDER_MSB) - { - UART_MSB_FIRST_ENABLE(&uart->huart); - } - else - { - UART_MSB_FIRST_DISABLE(&uart->huart); - } - - if (cfg->invert == NRZ_INVERTED) - { - UART_DATA_INV_ENABLE(&uart->huart); - } - else - { - UART_DATA_INV_DISABLE(&uart->huart); - } - - return RT_EOK; -} - -static rt_err_t es32f3x_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - - uart = (struct es32_uart *)serial->parent.user_data; - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irq); - /* disable interrupt */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, DISABLE); - break; - - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irq); - /* enable interrupt */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, ENABLE); - break; - } - - return RT_EOK; -} - -static int es32f3x_putc(struct rt_serial_device *serial, char c) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - while (ald_uart_get_status(&uart->huart, UART_STATUS_TFEMPTY) == RESET) - ; - WRITE_REG(uart->huart.perh->TXBUF, c); - - return 1; -} - -static int es32f3x_getc(struct rt_serial_device *serial) -{ - int ch = -1; - struct es32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - if (ald_uart_get_status(&uart->huart, UART_STATUS_RFTH)) - { - ch = (uint8_t)(uart->huart.perh->RXBUF & 0xFF); - } - - return ch; -} - -static const struct rt_uart_ops es32f3x_uart_ops = -{ - es32f3x_configure, - es32f3x_control, - es32f3x_putc, - es32f3x_getc, -}; - #ifdef BSP_USING_UART0 /* UART0 device driver structure */ struct es32_uart uart0 = @@ -353,18 +186,243 @@ void UART5_Handler(void) } #endif /* BSP_USING_UART5 */ +static rt_err_t es32f3x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + gpio_init_t gpio_initstructure; + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + /* Initialize tx pin */ + gpio_initstructure.mode = GPIO_MODE_OUTPUT; + gpio_initstructure.odos = GPIO_PUSH_PULL; + gpio_initstructure.pupd = GPIO_PUSH_UP; + gpio_initstructure.podrv = GPIO_OUT_DRIVE_1; + gpio_initstructure.nodrv = GPIO_OUT_DRIVE_1; + gpio_initstructure.flt = GPIO_FILTER_DISABLE; + gpio_initstructure.type = GPIO_TYPE_TTL; + +#ifdef BSP_USING_UART0 + if(uart == (&uart0)) + { +#if defined(ES_UART0_TX_GPIO_FUNC)&&defined(ES_UART0_TX_GPIO_PORT)&&defined(ES_UART0_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART0_TX_GPIO_FUNC; + ald_gpio_init(ES_UART0_TX_GPIO_PORT, ES_UART0_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART0_RX_GPIO_FUNC)&&defined(ES_UART0_RX_GPIO_PORT)&&defined(ES_UART0_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART0_RX_GPIO_FUNC; + ald_gpio_init(ES_UART0_RX_GPIO_PORT, ES_UART0_RX_GPIO_PIN, &gpio_initstructure); +#endif + ald_cmu_perh_clock_config(CMU_PERH_UART0, ENABLE); + } + +#endif /* uart0 gpio init */ + +#ifdef BSP_USING_UART1 + if(uart == (&uart1)) + { +#if defined(ES_UART1_TX_GPIO_FUNC)&&defined(ES_UART1_TX_GPIO_PORT)&&defined(ES_UART1_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART1_TX_GPIO_FUNC; + ald_gpio_init(ES_UART1_TX_GPIO_PORT, ES_UART1_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART1_RX_GPIO_FUNC)&&defined(ES_UART1_RX_GPIO_PORT)&&defined(ES_UART1_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART1_RX_GPIO_FUNC; + ald_gpio_init(ES_UART1_RX_GPIO_PORT, ES_UART1_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART1, ENABLE); + } +#endif /* uart1 gpio init */ + +#ifdef BSP_USING_UART2 + if(uart == (&uart2)) + { +#if defined(ES_UART2_TX_GPIO_FUNC)&&defined(ES_UART2_TX_GPIO_PORT)&&defined(ES_UART2_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART2_TX_GPIO_FUNC; + ald_gpio_init(ES_UART2_TX_GPIO_PORT, ES_UART2_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART2_RX_GPIO_FUNC)&&defined(ES_UART2_RX_GPIO_PORT)&&defined(ES_UART2_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART2_RX_GPIO_FUNC; + ald_gpio_init(ES_UART2_RX_GPIO_PORT, ES_UART2_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART2, ENABLE); + } +#endif /* uart2 gpio init */ + +#ifdef BSP_USING_UART3 + if(uart == (&uart3)) + { +#if defined(ES_UART3_TX_GPIO_FUNC)&&defined(ES_UART3_TX_GPIO_PORT)&&defined(ES_UART3_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART3_TX_GPIO_FUNC; + ald_gpio_init(ES_UART3_TX_GPIO_PORT, ES_UART3_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART3_RX_GPIO_FUNC)&&defined(ES_UART3_RX_GPIO_PORT)&&defined(ES_UART3_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART3_RX_GPIO_FUNC; + ald_gpio_init(ES_UART3_RX_GPIO_PORT, ES_UART3_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART3, ENABLE); + } +#endif /* uart3 gpio init */ + +#ifdef BSP_USING_UART4 + if(uart == (&uart4)) + { +#if defined(ES_UART4_TX_GPIO_FUNC)&&defined(ES_UART4_TX_GPIO_PORT)&&defined(ES_UART4_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART4_TX_GPIO_FUNC; + ald_gpio_init(ES_UART4_TX_GPIO_PORT, ES_UART4_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART4_RX_GPIO_FUNC)&&defined(ES_UART4_RX_GPIO_PORT)&&defined(ES_UART4_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART4_RX_GPIO_FUNC; + ald_gpio_init(ES_UART4_RX_GPIO_PORT, ES_UART4_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART4, ENABLE); + } +#endif /* uart4 gpio init */ + +#ifdef BSP_USING_UART5 + if(uart == (&uart5)) + { +#if defined(ES_UART5_TX_GPIO_FUNC)&&defined(ES_UART5_TX_GPIO_PORT)&&defined(ES_UART5_TX_GPIO_PIN) + gpio_initstructure.func = ES_UART5_TX_GPIO_FUNC; + ald_gpio_init(ES_UART5_TX_GPIO_PORT, ES_UART5_TX_GPIO_PIN, &gpio_initstructure); +#endif + +#if defined(ES_UART5_RX_GPIO_FUNC)&&defined(ES_UART5_RX_GPIO_PORT)&&defined(ES_UART5_RX_GPIO_PIN) + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + gpio_initstructure.func = ES_UART5_RX_GPIO_FUNC; + ald_gpio_init(ES_UART5_RX_GPIO_PORT, ES_UART5_RX_GPIO_PIN, &gpio_initstructure); +#endif + + ald_cmu_perh_clock_config(CMU_PERH_UART5, ENABLE); + } +#endif /* uart5 gpio init */ + + ald_uart_tx_fifo_config(&uart->huart, UART_TXFIFO_EMPTY); + ald_uart_rx_fifo_config(&uart->huart, UART_RXFIFO_1BYTE); + + uart->huart.init.mode = UART_MODE_UART; + uart->huart.init.baud = cfg->baud_rate; + uart->huart.init.word_length = (uart_word_length_t)(8 - cfg->data_bits); + uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); + uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; + uart->huart.init.stop_bits = UART_STOP_BITS_1; + ald_uart_init(&uart->huart); + + if (cfg->bit_order == BIT_ORDER_MSB) + { + UART_MSB_FIRST_ENABLE(&uart->huart); + } + else + { + UART_MSB_FIRST_DISABLE(&uart->huart); + } + + if (cfg->invert == NRZ_INVERTED) + { + UART_DATA_INV_ENABLE(&uart->huart); + } + else + { + UART_DATA_INV_DISABLE(&uart->huart); + } + + return RT_EOK; +} + +static rt_err_t es32f3x_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = (struct es32_uart *)serial->parent.user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + /* disable interrupt */ + ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, DISABLE); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + /* enable interrupt */ + ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, ENABLE); + break; + } + + return RT_EOK; +} + +static int es32f3x_putc(struct rt_serial_device *serial, char c) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + while (ald_uart_get_status(&uart->huart, UART_STATUS_TFEMPTY) == RESET) + ; + WRITE_REG(uart->huart.perh->TXBUF, c); + + return 1; +} + +static int es32f3x_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct es32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + if (ald_uart_get_status(&uart->huart, UART_STATUS_RFTH)) + { + ch = (uint8_t)(uart->huart.perh->RXBUF & 0xFF); + } + + return ch; +} + +static const struct rt_uart_ops es32f3x_uart_ops = +{ + es32f3x_configure, + es32f3x_control, + es32f3x_putc, + es32f3x_getc, +}; + int rt_hw_uart_init(void) { struct es32_uart *uart; - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #ifdef BSP_USING_UART0 uart = &uart0; serial0.ops = &es32f3x_uart_ops; - serial0.config = config; + serial0.config = (struct serial_configure)ES_UART0_CONFIG; /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", + rt_hw_serial_register(&serial0, ES_DEVICE_NAME_UART0, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART0 */ @@ -372,10 +430,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART1 uart = &uart1; serial1.ops = &es32f3x_uart_ops; - serial1.config = config; + serial1.config = (struct serial_configure)ES_UART1_CONFIG; /* register UART1 device */ - rt_hw_serial_register(&serial1, "uart1", + rt_hw_serial_register(&serial1, ES_DEVICE_NAME_UART1, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART1 */ @@ -383,10 +441,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART2 uart = &uart2; serial2.ops = &es32f3x_uart_ops; - serial2.config = config; + serial2.config = (struct serial_configure)ES_UART2_CONFIG; /* register UART2 device */ - rt_hw_serial_register(&serial2, "uart2", + rt_hw_serial_register(&serial2, ES_DEVICE_NAME_UART2, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART2 */ @@ -394,10 +452,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART3 uart = &uart3; serial3.ops = &es32f3x_uart_ops; - serial3.config = config; + serial3.config = (struct serial_configure)ES_UART3_CONFIG; /* register UART3 device */ - rt_hw_serial_register(&serial3, "uart3", + rt_hw_serial_register(&serial3, ES_DEVICE_NAME_UART3, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART3 */ @@ -405,10 +463,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART4 uart = &uart4; serial4.ops = &es32f3x_uart_ops; - serial4.config = config; + serial4.config = (struct serial_configure)ES_UART4_CONFIG; /* register UART4 device */ - rt_hw_serial_register(&serial4, "uart4", + rt_hw_serial_register(&serial4, ES_DEVICE_NAME_UART4, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART4 */ @@ -416,10 +474,10 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART5 uart = &uart5; serial5.ops = &es32f3x_uart_ops; - serial5.config = config; + serial5.config = (struct serial_configure)ES_UART5_CONFIG; /* register UART5 device */ - rt_hw_serial_register(&serial5, "uart5", + rt_hw_serial_register(&serial5, ES_DEVICE_NAME_UART5, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* BSP_USING_UART5 */ diff --git a/bsp/essemi/es32f369x/drivers/drv_uart.h b/bsp/essemi/es32f369x/drivers/drv_uart.h index fed3184080..6e9b7703e0 100644 --- a/bsp/essemi/es32f369x/drivers/drv_uart.h +++ b/bsp/essemi/es32f369x/drivers/drv_uart.h @@ -3,6 +3,18 @@ * * SPDX-License-Identifier: Apache-2.0 * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * Change Logs: * Date Author Notes * 2020-01-14 wangyq the first version diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h index 2e29a0d583..71e4e83261 100644 --- a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S new file mode 100644 index 0000000000..4e34d42c1d --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S @@ -0,0 +1,438 @@ +/** + ****************************************************************************** + * @file startup_es32f36xx.s + * @author AE Team + * @brief ES32F36xx devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + */ + + .syntax unified + .arch armv7-m + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/*bl __libc_init_array + + bl main */ + bl entry + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack /* 0, load top of stack */ + .word Reset_Handler /* 1, reset handler */ + .word NMI_Handler /* 2, nmi handler */ + .word HardFault_Handler /* 3, hard fault handler */ + .word MemManage_Handler /* 4, MPU Fault Handler */ + .word BusFault_Handler /* 5, Bus Fault Handler */ + .word UsageFault_Handler /* 6, Usage Fault Handler */ + .word 0 /* 7, Reserved */ + .word 0 /* 8, Reserved */ + .word 0 /* 9, Reserved */ + .word 0 /* 10, Reserved */ + .word SVC_Handler /* 11, svcall handler */ + .word DebugMon_Handler /* 12, Debug Monitor Handler */ + .word 0 /* 13, Reserved */ + .word PendSV_Handler /* 14, pendsv handler */ + .word SysTick_Handler /* 15, systick handler */ + .word WWDG_Handler /* 16, irq0 WWDG handler */ + .word IWDG_Handler /* 17, irq1 IWDG handler */ + .word LVD_Handler /* 18, irq2 LVD handler */ + .word RTC_Handler /* 19, irq3 RTC handler */ + .word 0 /* 20, irq4 Reserved */ + .word 0 /* 21, irq5 Reserved */ + .word CMU_Handler /* 22, irq6 CMU handler */ + .word ADC0_Handler /* 23, irq7 ADC0 handler */ + .word CAN0_TX_Handler /* 24, irq8 CAN0_TX handler */ + .word CAN0_RX0_Handler /* 25, irq9 CAN0_RX0 handler */ + .word CAN0_RX1_Handler /* 26, irq10 CAN0_RX1 handler */ + .word CAN0_EXCEPTION_Handler /* 27, irq11 CAN0_EXCEPTION handler */ + .word AD16C4T0_BRK_Handler /* 28, irq12 AD16C4T0_BRK handler */ + .word AD16C4T0_UP_Handler /* 29, irq13 AD16C4T0_UP handler */ + .word AD16C4T0_TRIG_COM_Handler /* 30, irq14 AD16C4T0_TRIG_COM handler */ + .word AD16C4T0_CC_Handler /* 31, irq15 AD16C4T0_CC handler */ + .word AD16C4T1_BRK_Handler /* 32, irq16 AD16C4T1_BRK handler */ + .word AD16C4T1_UP_Handler /* 33, irq17 AD16C4T1_UP handler */ + .word AD16C4T1_TRIG_COM_Handler /* 34, irq18 AD16C4T1_TRIG_COM handler */ + .word AD16C4T1_CC_Handler /* 35, irq19 AD16C4T1_CC handler */ + .word GP32C4T0_Handler /* 36, irq20 GP32C4T0 handler */ + .word GP32C4T1_Handler /* 37, irq21 GP32C4T1 handler */ + .word BS16T0_Handler /* 38, irq22 BS16T0 handler */ + .word BS16T1_Handler /* 39, irq23 BS16T1 handler */ + .word GP16C4T0_Handler /* 40, irq24 GP16C4T0 handler */ + .word GP16C4T1_Handler /* 41, irq25 GP16C4T1 handler */ + .word 0 /* 42, irq26 Reserved */ + .word DAC0_CH0_Handler /* 43, irq27 DAC0_CH0 handler */ + .word I2C0_EV_Handler /* 44, irq28 I2C0_EV handler */ + .word I2C0_ERR_Handler /* 45, irq29 I2C0_ERR handler */ + .word I2C1_EV_Handler /* 46 irq30 I2C1_EV handler */ + .word I2C1_ERR_Handler /* 47, irq31 I2C1_ERR handler */ + .word SPI0_I2S0_Handler /* 48, irq32 SPI0_I2S0 handler */ + .word SPI1_I2S1_Handler /* 49, irq33 SPI1_I2S1 handler */ + .word UART0_Handler /* 50, irq34 UART0 handler */ + .word UART1_Handler /* 51, irq35 UART1 handler */ + .word UART2_Handler /* 52, irq36 UART2 handler */ + .word UART3_Handler /* 53, irq37 UART3 handler */ + .word UART4_Handler /* 54, irq38 UART4 handler */ + .word UART5_Handler /* 55, irq39 UART5 handler */ + .word 0 /* 56, irq40 Reserved */ + .word 0 /* 57, irq41 Reserved */ + .word CRYPT_Handler /* 58, irq42 CRYPT handler */ + .word ACMP0_Handler /* 59, irq43 ACMP0 handler */ + .word ACMP1_Handler /* 60, irq44 ACMP1 handler */ + .word SPI2_I2S2_Handler /* 61, irq45 SPI2_I2S2 handler */ + .word 0 /* 62, irq46 Reserved */ + .word EBI_Handler /* 63, irq47 EBI handler */ + .word TRNG_Handler /* 64, irq48 TRNG handler */ + .word TSENSE_Handler /* 65, irq49 TSENSE handler */ + .word EXTI0_Handler /* 66, irq50 EXTI0 handler */ + .word EXTI1_Handler /* 67, irq51 EXTI1 handler */ + .word EXTI2_Handler /* 68, irq52 EXTI2 handler */ + .word EXTI3_Handler /* 69, irq53 EXTI3 handler */ + .word EXTI4_Handler /* 70, irq54 EXTI4 handler */ + .word EXTI5_Handler /* 71, irq55 EXTI5 handler */ + .word EXTI6_Handler /* 72, irq56 EXTI6 handler */ + .word EXTI7_Handler /* 73, irq57 EXTI7 handler */ + .word EXTI8_Handler /* 74, irq58 EXTI8 handler */ + .word EXTI9_Handler /* 75, irq59 EXTI9 handler */ + .word EXTI10_Handler /* 76, irq60 EXTI10 handler */ + .word EXTI11_Handler /* 77, irq61 EXTI11 handler */ + .word EXTI12_Handler /* 78, irq62 EXTI12 handler */ + .word EXTI13_Handler /* 79, irq63 EXTI13 handler */ + .word EXTI14_Handler /* 80, irq64 EXTI14 handler */ + .word EXTI15_Handler /* 81, irq65 EXTI15 handler */ + .word DMA_Handler /* 82, irq66 DMA handler */ + .word ADC1_Handler /* 83, irq67 ADC1 handler */ + .word DAC0_CH1_Handler /* 84, irq68 DAC0_CH1 handler */ + .word QSPI_Handler /* 85, irq69 QSPI handler */ + .word USB_INT_Handler /* 86, irq70 USB_INT handler */ + .word USB_DMA_Handler /* 87, irq71 USB_DMA handler */ + .word ACMP2_Handler /* 88, irq72 ACMP2 handler */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_Handler + .thumb_set WWDG_Handler,Default_Handler + + .weak IWDG_Handler + .thumb_set IWDG_Handler,Default_Handler + + .weak LVD_Handler + .thumb_set LVD_Handler,Default_Handler + + .weak RTC_Handler + .thumb_set RTC_Handler,Default_Handler + + .weak CMU_Handler + .thumb_set CMU_Handler,Default_Handler + + .weak ADC0_Handler + .thumb_set ADC0_Handler,Default_Handler + + .weak CAN0_TX_Handler + .thumb_set CAN0_TX_Handler,Default_Handler + + .weak CAN0_RX0_Handler + .thumb_set CAN0_RX0_Handler,Default_Handler + + .weak CAN0_RX1_Handler + .thumb_set CAN0_RX1_Handler,Default_Handler + + .weak CAN0_EXCEPTION_Handler + .thumb_set CAN0_EXCEPTION_Handler,Default_Handler + + .weak AD16C4T0_BRK_Handler + .thumb_set AD16C4T0_BRK_Handler,Default_Handler + + .weak AD16C4T0_UP_Handler + .thumb_set AD16C4T0_UP_Handler,Default_Handler + + .weak AD16C4T0_TRIG_COM_Handler + .thumb_set AD16C4T0_TRIG_COM_Handler,Default_Handler + + .weak AD16C4T0_CC_Handler + .thumb_set AD16C4T0_CC_Handler,Default_Handler + + .weak AD16C4T1_BRK_Handler + .thumb_set AD16C4T1_BRK_Handler,Default_Handler + + .weak AD16C4T1_UP_Handler + .thumb_set AD16C4T1_UP_Handler,Default_Handler + + .weak AD16C4T1_TRIG_COM_Handler + .thumb_set AD16C4T1_TRIG_COM_Handler,Default_Handler + + .weak AD16C4T1_CC_Handler + .thumb_set AD16C4T1_CC_Handler,Default_Handler + + .weak GP32C4T0_Handler + .thumb_set GP32C4T0_Handler,Default_Handler + + .weak GP32C4T1_Handler + .thumb_set GP32C4T1_Handler,Default_Handler + + .weak BS16T0_Handler + .thumb_set BS16T0_Handler,Default_Handler + + .weak BS16T1_Handler + .thumb_set BS16T1_Handler,Default_Handler + + .weak GP16C4T0_Handler + .thumb_set GP16C4T0_Handler,Default_Handler + + .weak GP16C4T1_Handler + .thumb_set GP16C4T1_Handler,Default_Handler + + .weak DAC0_CH0_Handler + .thumb_set DAC0_CH0_Handler,Default_Handler + + .weak I2C0_EV_Handler + .thumb_set I2C0_EV_Handler,Default_Handler + + .weak I2C0_ERR_Handler + .thumb_set I2C0_ERR_Handler,Default_Handler + + .weak I2C1_EV_Handler + .thumb_set I2C1_EV_Handler,Default_Handler + + .weak I2C1_ERR_Handler + .thumb_set I2C1_ERR_Handler,Default_Handler + + .weak SPI0_I2S0_Handler + .thumb_set SPI0_I2S0_Handler,Default_Handler + + .weak SPI1_I2S1_Handler + .thumb_set SPI1_I2S1_Handler,Default_Handler + + .weak UART0_Handler + .thumb_set UART0_Handler,Default_Handler + + .weak UART1_Handler + .thumb_set UART1_Handler,Default_Handler + + .weak UART2_Handler + .thumb_set UART2_Handler,Default_Handler + + .weak UART3_Handler + .thumb_set UART3_Handler,Default_Handler + + .weak UART4_Handler + .thumb_set UART4_Handler,Default_Handler + + .weak UART5_Handler + .thumb_set UART5_Handler,Default_Handler + + .weak CRYPT_Handler + .thumb_set CRYPT_Handler,Default_Handler + + .weak ACMP0_Handler + .thumb_set ACMP0_Handler,Default_Handler + + .weak ACMP1_Handler + .thumb_set ACMP1_Handler,Default_Handler + + .weak SPI2_I2S2_Handler + .thumb_set SPI2_I2S2_Handler,Default_Handler + + .weak EBI_Handler + .thumb_set EBI_Handler,Default_Handler + + .weak TRNG_Handler + .thumb_set TRNG_Handler,Default_Handler + + .weak TSENSE_Handler + .thumb_set TSENSE_Handler,Default_Handler + + .weak EXTI0_Handler + .thumb_set EXTI0_Handler,Default_Handler + + .weak EXTI1_Handler + .thumb_set EXTI1_Handler,Default_Handler + + .weak EXTI2_Handler + .thumb_set EXTI2_Handler,Default_Handler + + .weak EXTI3_Handler + .thumb_set EXTI3_Handler,Default_Handler + + .weak EXTI4_Handler + .thumb_set EXTI4_Handler,Default_Handler + + .weak EXTI5_Handler + .thumb_set EXTI5_Handler,Default_Handler + + .weak EXTI6_Handler + .thumb_set EXTI6_Handler,Default_Handler + + .weak EXTI7_Handler + .thumb_set EXTI7_Handler,Default_Handler + + .weak EXTI8_Handler + .thumb_set EXTI8_Handler,Default_Handler + + .weak EXTI9_Handler + .thumb_set EXTI9_Handler,Default_Handler + + .weak EXTI10_Handler + .thumb_set EXTI10_Handler,Default_Handler + + .weak EXTI11_Handler + .thumb_set EXTI11_Handler,Default_Handler + + .weak EXTI12_Handler + .thumb_set EXTI12_Handler,Default_Handler + + .weak EXTI13_Handler + .thumb_set EXTI13_Handler,Default_Handler + + .weak EXTI14_Handler + .thumb_set EXTI14_Handler,Default_Handler + + .weak EXTI15_Handler + .thumb_set EXTI15_Handler,Default_Handler + + .weak DMA_Handler + .thumb_set DMA_Handler,Default_Handler + + .weak ADC1_Handler + .thumb_set ADC1_Handler,Default_Handler + + .weak DAC0_CH1_Handler + .thumb_set DAC0_CH1_Handler,Default_Handler + + .weak QSPI_Handler + .thumb_set QSPI_Handler,Default_Handler + + .weak USB_INT_Handler + .thumb_set USB_INT_Handler,Default_Handler + + .weak USB_DMA_Handler + .thumb_set USB_DMA_Handler,Default_Handler + + .weak ACMP2_Handler + .thumb_set ACMP2_Handler,Default_Handler + diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s index 362c8483fe..c8aaf3ed69 100644 --- a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s @@ -4,6 +4,20 @@ ; author : AE Team ; data : 23 Jan 2019 ; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. ;******************************************************************************* ;Stack Configuration------------------------------------------------------------ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h index 7fbb68e655..60877098d6 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h index 2638e139fd..e88c16d10b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h @@ -9,6 +9,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ****************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h index ce23ba73e9..246f6397d3 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h index bd861b2d04..e14ff7851e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h index 196094eaaa..04a5d5ef5e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ****************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h index 400551ae45..55d713ed38 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h index 1ee5597055..4953ab4f14 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h index dcd6761acb..4e0f3cc152 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h index f72cb06fc7..36a4d41387 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h index d086905826..0e71f3e7e0 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h @@ -9,6 +9,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ****************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h index 4d72f6cb2b..c6471b2c2c 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h @@ -10,6 +10,21 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h index efd366889c..6f29a0cc7b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h index a4c0f372d6..d3ed85d97a 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h index 3a1dfac113..8899ca4326 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h index 4731c34a67..517330ce32 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h index 7219542d60..c520c3d41a 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h index 46d0c36c8e..e6a811aae3 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h index 900cc43086..cb1e0bf023 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h index bf08b7de80..89d8d5875b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h index 83a200b34e..9815aa6ebc 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h index 992b3790f0..39f481a5be 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h index d58c34db24..f400be8a9f 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h index a8e80b09d8..f4e2642dcd 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h @@ -7,6 +7,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h index 07319306b0..bb3ec3df89 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h index 4c31312e84..3234aa7d6e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h index 55cbbfec47..6faecf5145 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h index 63a4a01f56..ebda1db3a7 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h index 2743b83535..aff23692a3 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h index c541c714ed..35063a28a1 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h index 1805c3f95a..dcbc884368 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h index ff86dbbcbf..267a7db0da 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h index 6aff4435b1..cceb2587ec 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h index a525f59783..56c1b5b94d 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h index 38c991a757..d319f7a575 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h index 5629fafaa3..805be32d50 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h index ea5bd88970..a8db397a97 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ @@ -22,7 +36,7 @@ extern "C" { #endif #include - +#include "es_conf_info_select.h" #if defined (__CC_ARM) #define __INLINE__ __inline diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h index 1c6b1b942f..b5589ce07a 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c index 75c53bda13..2e2dbe74d5 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c index c239d074b2..6870742cc0 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c @@ -24,6 +24,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c index c0a5e86f8a..568f7cec0e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c index 7a00c641fb..a49d150e32 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c index 24cabd8cef..ec9ec28260 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c @@ -14,6 +14,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c index 76c6e516be..8beb08de5b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c @@ -9,7 +9,21 @@ * @author AE Team * @note * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ********************************************************************************* * @verbatim diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c index ad0199a486..ea64ad1245 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c index 4d17afca3b..04a0fa19de 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c index ba07048b07..7f98ce0b88 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c @@ -10,6 +10,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c index a314e72b29..eae14f80c3 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c index 5fc69ba3f9..d58acdfc9b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. ****************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c index 48c7fe0228..33b114fa55 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * ********************************************************************************* diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c index 0c8f94b3a2..07d7dc5f60 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * ********************************************************************************* diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c index 686bb601d2..255c569463 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c @@ -16,6 +16,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== @@ -185,7 +199,7 @@ void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) for (i = 0; i < 16; ++i) { if (((pin >> i) & 0x1) == 0) continue; - + /* Get position and 2-bits mask */ pos = i << 1; mask = 0x3 << pos; diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c index 419bb25481..37ec31d67d 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c @@ -10,6 +10,20 @@ * @note * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c index 9570ddf8f7..c018037845 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c index e350c0a3ac..a2265bc1dc 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c index 1595d520e6..cc178feb7f 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c index 4d52faee86..ca28cbf091 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c index e26037fcfc..3546c0b3be 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c index bb588747db..0d411b0bbd 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c index d0c0ecb3ac..b8bd90ffc1 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ #include "ald_qspi.h" diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c index c5bd06b325..55869f621b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c index c0fd24b64f..baf3e5d205 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c @@ -18,6 +18,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c index c423f657cb..684e1eb5e8 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ******************************************************************************** */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c index ce78e605a7..470167d65e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c index 31f7491679..384175d117 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ #include "ald_sram.h" diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c index 49e8ccee2c..7860499237 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c @@ -12,6 +12,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c index 200f8db8bc..54496cec18 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c index b5bbc8534b..90c341c864 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c index f747967e32..84c96348c6 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c @@ -17,6 +17,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* * @verbatim ============================================================================== diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c index 26605cd791..3524853e37 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c index 1e69e95d8f..2077cdabed 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ #include "ald_conf.h" diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c index bd247fc055..d2c5bfecb6 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c @@ -11,6 +11,20 @@ * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ********************************************************************************* */ diff --git a/bsp/essemi/es32f369x/project.uvoptx b/bsp/essemi/es32f369x/project.uvoptx index 9820d88eaa..2ee2601b40 100644 --- a/bsp/essemi/es32f369x/project.uvoptx +++ b/bsp/essemi/es32f369x/project.uvoptx @@ -73,7 +73,7 @@ 0 - 1 + 0 0 1 @@ -176,7 +176,7 @@ Applications - 1 + 0 0 0 0 @@ -195,7 +195,7 @@ - cpu + CPU 0 0 0 @@ -275,8 +275,8 @@ 0 0 0 - ..\..\..\components\drivers\can\can.c - can.c + ..\..\..\components\drivers\misc\pin.c + pin.c 0 0 @@ -287,8 +287,8 @@ 0 0 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\components\drivers\serial\serial.c + serial.c 0 0 @@ -299,8 +299,8 @@ 0 0 0 - ..\..\..\components\drivers\i2c\i2c_core.c - i2c_core.c + ..\..\..\components\drivers\src\dataqueue.c + dataqueue.c 0 0 @@ -311,8 +311,8 @@ 0 0 0 - ..\..\..\components\drivers\i2c\i2c_dev.c - i2c_dev.c + ..\..\..\components\drivers\src\pipe.c + pipe.c 0 0 @@ -323,8 +323,8 @@ 0 0 0 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - i2c-bit-ops.c + ..\..\..\components\drivers\src\workqueue.c + workqueue.c 0 0 @@ -335,8 +335,8 @@ 0 0 0 - ..\..\..\components\drivers\misc\pin.c - pin.c + ..\..\..\components\drivers\src\completion.c + completion.c 0 0 @@ -347,8 +347,8 @@ 0 0 0 - ..\..\..\components\drivers\misc\adc.c - adc.c + ..\..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c 0 0 @@ -359,8 +359,8 @@ 0 0 0 - ..\..\..\components\drivers\misc\rt_drv_pwm.c - rt_drv_pwm.c + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c 0 0 @@ -371,239 +371,239 @@ 0 0 0 - ..\..\..\components\drivers\pm\pm.c - pm.c + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c 0 0 + + + + Drivers + 0 + 0 + 0 + 0 - 3 + 4 16 1 0 0 0 - ..\..\..\components\drivers\rtc\rtc.c - rtc.c + drivers\drv_gpio.c + drv_gpio.c 0 0 - 3 + 4 17 1 0 0 0 - ..\..\..\components\drivers\serial\serial.c - serial.c + drivers\drv_uart.c + drv_uart.c 0 0 - 3 + 4 18 1 0 0 0 - ..\..\..\components\drivers\spi\spi_core.c - spi_core.c + drivers\board.c + board.c 0 0 + + + + finsh + 0 + 0 + 0 + 0 - 3 + 5 19 1 0 0 0 - ..\..\..\components\drivers\spi\spi_dev.c - spi_dev.c + ..\..\..\components\finsh\shell.c + shell.c 0 0 - 3 + 5 20 1 0 0 0 - ..\..\..\components\drivers\src\completion.c - completion.c + ..\..\..\components\finsh\msh.c + msh.c 0 0 - 3 + 5 21 1 0 0 0 - ..\..\..\components\drivers\src\dataqueue.c - dataqueue.c + ..\..\..\components\finsh\cmd.c + cmd.c 0 0 + + + + Kernel + 0 + 0 + 0 + 0 - 3 + 6 22 1 0 0 0 - ..\..\..\components\drivers\src\pipe.c - pipe.c + ..\..\..\src\mem.c + mem.c 0 0 - 3 + 6 23 1 0 0 0 - ..\..\..\components\drivers\src\ringblk_buf.c - ringblk_buf.c + ..\..\..\src\irq.c + irq.c 0 0 - 3 + 6 24 1 0 0 0 - ..\..\..\components\drivers\src\ringbuffer.c - ringbuffer.c + ..\..\..\src\timer.c + timer.c 0 0 - 3 + 6 25 1 0 0 0 - ..\..\..\components\drivers\src\waitqueue.c - waitqueue.c + ..\..\..\src\object.c + object.c 0 0 - 3 + 6 26 1 0 0 0 - ..\..\..\components\drivers\src\workqueue.c - workqueue.c + ..\..\..\src\kservice.c + kservice.c 0 0 - - - - Drivers - 0 - 0 - 0 - 0 - 4 + 6 27 1 0 0 0 - drivers\board.c - board.c + ..\..\..\src\signal.c + signal.c 0 0 - 4 + 6 28 1 0 0 0 - drivers\drv_gpio.c - drv_gpio.c + ..\..\..\src\mempool.c + mempool.c 0 0 - 4 + 6 29 1 0 0 0 - drivers\drv_uart.c - drv_uart.c + ..\..\..\src\thread.c + thread.c 0 0 - - - - finsh - 0 - 0 - 0 - 0 - 5 + 6 30 1 0 0 0 - ..\..\..\components\finsh\shell.c - shell.c + ..\..\..\src\ipc.c + ipc.c 0 0 - 5 + 6 31 1 0 0 0 - ..\..\..\components\finsh\cmd.c - cmd.c + ..\..\..\src\idle.c + idle.c 0 0 - 5 + 6 32 1 0 0 0 - ..\..\..\components\finsh\msh.c - msh.c + ..\..\..\src\scheduler.c + scheduler.c 0 0 - - - - Kernel - 0 - 0 - 0 - 0 6 33 @@ -611,8 +611,8 @@ 0 0 0 - ..\..\..\src\clock.c - clock.c + ..\..\..\src\device.c + device.c 0 0 @@ -635,393 +635,401 @@ 0 0 0 - ..\..\..\src\device.c - device.c + ..\..\..\src\clock.c + clock.c 0 0 + + + + libc + 0 + 0 + 0 + 0 - 6 + 7 36 1 0 0 0 - ..\..\..\src\idle.c - idle.c + ..\..\..\components\libc\compilers\common\time.c + time.c 0 0 + + + + Libraries + 0 + 0 + 0 + 0 - 6 + 8 37 1 0 0 0 - ..\..\..\src\ipc.c - ipc.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c + ald_i2c.c 0 0 - 6 + 8 38 1 0 0 0 - ..\..\..\src\irq.c - irq.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c + ald_ebi.c 0 0 - 6 + 8 39 1 0 0 0 - ..\..\..\src\kservice.c - kservice.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c + ald_rtc.c 0 0 - 6 + 8 40 1 0 0 0 - ..\..\..\src\mem.c - mem.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c + ald_can.c 0 0 - 6 + 8 41 1 0 0 0 - ..\..\..\src\mempool.c - mempool.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c + ald_nor_lcd.c 0 0 - 6 + 8 42 1 0 0 0 - ..\..\..\src\object.c - object.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c + ald_cmu.c 0 0 - 6 + 8 43 1 0 0 0 - ..\..\..\src\scheduler.c - scheduler.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c + ald_pis.c 0 0 - 6 + 8 44 1 0 0 0 - ..\..\..\src\signal.c - signal.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c + ald_timer.c 0 0 - 6 + 8 45 1 0 0 0 - ..\..\..\src\thread.c - thread.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c + ald_sram.c 0 0 - 6 + 8 46 1 0 0 0 - ..\..\..\src\timer.c - timer.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c + ald_iap.c 0 0 - - - - Libraries - 0 - 0 - 0 - 0 - 7 + 8 47 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c - ald_acmp.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c + ald_wdt.c 0 0 - 7 + 8 48 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c - ald_adc.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c + ald_rtchw.c 0 0 - 7 + 8 49 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c - ald_bkpc.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c + ald_dac.c 0 0 - 7 + 8 50 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c - ald_calc.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c + ald_acmp.c 0 0 - 7 + 8 51 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c - ald_can.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c + ald_gpio.c 0 0 - 7 + 8 52 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c - ald_cmu.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c + ald_tsense.c 0 0 - 7 + 8 53 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c - ald_crc.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c + ald_dma.c 0 0 - 7 + 8 54 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c - ald_crypt.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c + ald_rmu.c 0 0 - 7 + 8 55 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c - ald_dac.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c + ald_trng.c 0 0 - 7 + 8 56 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c - ald_dma.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c + ald_spi.c 0 0 - 7 + 8 57 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c - ald_ebi.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c + ald_crc.c 0 0 - 7 + 8 58 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c - ald_flash.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c + ald_usb.c 0 0 - 7 + 8 59 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c - ald_flash_ext.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c + ald_calc.c 0 0 - 7 + 8 60 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c - ald_gpio.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c + utils.c 0 0 - 7 + 8 61 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c - ald_i2c.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c + ald_qspi.c 0 0 - 7 + 8 62 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c - ald_i2s.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c + ald_flash.c 0 0 - 7 + 8 63 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c - ald_iap.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c + ald_nand.c 0 0 - 7 + 8 64 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c - ald_nand.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c + ald_adc.c 0 0 - 7 + 8 65 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c - ald_nor_lcd.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c + ald_crypt.c 0 0 - 7 + 8 66 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c - ald_pis.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c + ald_uart.c 0 0 - 7 + 8 67 1 0 @@ -1033,170 +1041,50 @@ 0 - 7 + 8 68 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c - ald_qspi.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c + ald_bkpc.c 0 0 - 7 + 8 69 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c - ald_rmu.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + ald_flash_ext.c 0 0 - 7 + 8 70 - 1 + 2 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c - ald_rtc.c + libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s + startup_es32f36xx.s 0 0 - 7 + 8 71 1 0 0 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c - ald_rtchw.c - 0 - 0 - - - 7 - 72 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c - ald_spi.c - 0 - 0 - - - 7 - 73 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c - ald_sram.c - 0 - 0 - - - 7 - 74 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c - ald_timer.c - 0 - 0 - - - 7 - 75 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c - ald_trng.c - 0 - 0 - - - 7 - 76 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c - ald_tsense.c - 0 - 0 - - - 7 - 77 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c - ald_uart.c - 0 - 0 - - - 7 - 78 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c - ald_usb.c - 0 - 0 - - - 7 - 79 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c - ald_wdt.c - 0 - 0 - - - 7 - 80 - 1 - 0 - 0 - 0 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c - utils.c - 0 - 0 - - - 7 - 81 - 2 - 0 - 0 - 0 - libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s - startup_es32f36xx.s + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c + ald_i2s.c 0 0 diff --git a/bsp/essemi/es32f369x/project.uvprojx b/bsp/essemi/es32f369x/project.uvprojx index bca6765ef1..5fc8ec68b0 100644 --- a/bsp/essemi/es32f369x/project.uvprojx +++ b/bsp/essemi/es32f369x/project.uvprojx @@ -336,9 +336,9 @@ 0 - ES32F36xx + ES32F36xx, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND - applications;.;drivers;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;libraries\CMSIS\Device\EastSoft\ES32F36xx\Include;libraries\CMSIS\Include;libraries\ES32F36xx_ALD_StdPeriph_Driver\Include + applications;.;drivers\ES;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;libraries\CMSIS\Device\EastSoft\ES32F36xx\Include;libraries\CMSIS\Include;libraries\ES32F36xx_ALD_StdPeriph_Driver\Include @@ -390,7 +390,7 @@ - cpu + CPU backtrace.c @@ -421,155 +421,36 @@ DeviceDrivers - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 0 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - - - can.c - 1 - ..\..\..\components\drivers\can\can.c - - - hwtimer.c - 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c - - - i2c_core.c - 1 - ..\..\..\components\drivers\i2c\i2c_core.c - - - i2c_dev.c - 1 - ..\..\..\components\drivers\i2c\i2c_dev.c - - - i2c-bit-ops.c - 1 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - pin.c 1 ..\..\..\components\drivers\misc\pin.c - - adc.c - 1 - ..\..\..\components\drivers\misc\adc.c - - - rt_drv_pwm.c - 1 - ..\..\..\components\drivers\misc\rt_drv_pwm.c - - - pm.c - 1 - ..\..\..\components\drivers\pm\pm.c - - - rtc.c - 1 - ..\..\..\components\drivers\rtc\rtc.c - serial.c 1 ..\..\..\components\drivers\serial\serial.c - spi_core.c - 1 - ..\..\..\components\drivers\spi\spi_core.c - - - spi_dev.c + dataqueue.c 1 - ..\..\..\components\drivers\spi\spi_dev.c + ..\..\..\components\drivers\src\dataqueue.c - completion.c + pipe.c 1 - ..\..\..\components\drivers\src\completion.c + ..\..\..\components\drivers\src\pipe.c - dataqueue.c + workqueue.c 1 - ..\..\..\components\drivers\src\dataqueue.c + ..\..\..\components\drivers\src\workqueue.c - pipe.c + completion.c 1 - ..\..\..\components\drivers\src\pipe.c + ..\..\..\components\drivers\src\completion.c ringblk_buf.c @@ -586,21 +467,11 @@ 1 ..\..\..\components\drivers\src\waitqueue.c - - workqueue.c - 1 - ..\..\..\components\drivers\src\workqueue.c - Drivers - - board.c - 1 - drivers\board.c - drv_gpio.c 1 @@ -611,6 +482,11 @@ 1 drivers\drv_uart.c + + board.c + 1 + drivers\board.c + @@ -622,14 +498,14 @@ ..\..\..\components\finsh\shell.c - cmd.c + msh.c 1 - ..\..\..\components\finsh\cmd.c + ..\..\..\components\finsh\msh.c - msh.c + cmd.c 1 - ..\..\..\components\finsh\msh.c + ..\..\..\components\finsh\cmd.c @@ -637,54 +513,54 @@ Kernel - clock.c + mem.c 1 - ..\..\..\src\clock.c + ..\..\..\src\mem.c - components.c + irq.c 1 - ..\..\..\src\components.c + ..\..\..\src\irq.c - device.c + timer.c 1 - ..\..\..\src\device.c + ..\..\..\src\timer.c - idle.c + object.c 1 - ..\..\..\src\idle.c + ..\..\..\src\object.c - ipc.c + kservice.c 1 - ..\..\..\src\ipc.c + ..\..\..\src\kservice.c - irq.c + signal.c 1 - ..\..\..\src\irq.c + ..\..\..\src\signal.c - kservice.c + mempool.c 1 - ..\..\..\src\kservice.c + ..\..\..\src\mempool.c - mem.c + thread.c 1 - ..\..\..\src\mem.c + ..\..\..\src\thread.c - mempool.c + ipc.c 1 - ..\..\..\src\mempool.c + ..\..\..\src\ipc.c - object.c + idle.c 1 - ..\..\..\src\object.c + ..\..\..\src\idle.c scheduler.c @@ -692,44 +568,49 @@ ..\..\..\src\scheduler.c - signal.c + device.c 1 - ..\..\..\src\signal.c + ..\..\..\src\device.c - thread.c + components.c 1 - ..\..\..\src\thread.c + ..\..\..\src\components.c - timer.c + clock.c 1 - ..\..\..\src\timer.c + ..\..\..\src\clock.c - Libraries + libc - ald_acmp.c + time.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c + ..\..\..\components\libc\compilers\common\time.c + + + + Libraries + - ald_adc.c + ald_i2c.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c - ald_bkpc.c + ald_ebi.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c - ald_calc.c + ald_rtc.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c ald_can.c @@ -737,129 +618,129 @@ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c - ald_cmu.c + ald_nor_lcd.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c - ald_crc.c + ald_cmu.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c - ald_crypt.c + ald_pis.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c - ald_dac.c + ald_timer.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c - ald_dma.c + ald_sram.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c - ald_ebi.c + ald_iap.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c - ald_flash.c + ald_wdt.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c - ald_flash_ext.c + ald_rtchw.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c - ald_gpio.c + ald_dac.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c - ald_i2c.c + ald_acmp.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c - ald_i2s.c + ald_gpio.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c - ald_iap.c + ald_tsense.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c - ald_nand.c + ald_dma.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c - ald_nor_lcd.c + ald_rmu.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c - ald_pis.c + ald_trng.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c - ald_pmu.c + ald_spi.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c - ald_qspi.c + ald_crc.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c - ald_rmu.c + ald_usb.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c - ald_rtc.c + ald_calc.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c - ald_rtchw.c + utils.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c - ald_spi.c + ald_qspi.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c - ald_sram.c + ald_flash.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c - ald_timer.c + ald_nand.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c - ald_trng.c + ald_adc.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c - ald_tsense.c + ald_crypt.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c ald_uart.c @@ -867,25 +748,30 @@ libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c - ald_usb.c + ald_pmu.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c - ald_wdt.c + ald_bkpc.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c - utils.c + ald_flash_ext.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c startup_es32f36xx.s 2 libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s + + ald_i2s.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c + diff --git a/bsp/essemi/es32f369x/rtconfig.h b/bsp/essemi/es32f369x/rtconfig.h index 54bd07901b..819056462c 100644 --- a/bsp/essemi/es32f369x/rtconfig.h +++ b/bsp/essemi/es32f369x/rtconfig.h @@ -15,7 +15,7 @@ #define RT_USING_HOOK #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 #define RT_DEBUG #define RT_DEBUG_COLOR @@ -26,6 +26,7 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +#define RT_USING_SIGNALS /* Memory Management */ @@ -76,22 +77,14 @@ #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_CAN -#define RT_USING_HWTIMER -#define RT_USING_I2C -#define RT_USING_I2C_BITOPS #define RT_USING_PIN -#define RT_USING_ADC -#define RT_USING_PWM -#define RT_USING_PM -#define RT_USING_RTC -#define RT_USING_SPI /* Using USB */ /* POSIX layer and C standard library */ +#define RT_LIBC_USING_TIME /* Network */ @@ -144,6 +137,9 @@ /* system packages */ +/* Micrium: Micrium software products porting for RT-Thread */ + + /* peripheral libraries and drivers */ @@ -152,6 +148,9 @@ /* samples: kernel and components samples */ + +/* games: games run on RT-Thread console */ + #define SOC_ES32F3696LT /* Hardware Drivers Config */ @@ -179,7 +178,7 @@ /* RTC Drivers */ -/* HWtimer Drivers */ +/* HWTIMER Drivers */ /* PWM Drivers */ diff --git a/bsp/essemi/es32f369x/template.uvoptx b/bsp/essemi/es32f369x/template.uvoptx index 8d3f54f7f5..8e6583c22c 100644 --- a/bsp/essemi/es32f369x/template.uvoptx +++ b/bsp/essemi/es32f369x/template.uvoptx @@ -101,7 +101,9 @@ 0 0 1 - 2 + 0 + 0 + 3 @@ -165,6 +167,10 @@ + + + + diff --git a/bsp/essemi/es32f369x/template.uvprojx b/bsp/essemi/es32f369x/template.uvprojx index ad28753eb3..df9bb4e30c 100644 --- a/bsp/essemi/es32f369x/template.uvprojx +++ b/bsp/essemi/es32f369x/template.uvprojx @@ -10,11 +10,13 @@ rt-thread 0x4 ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 ES32F3696LT Eastsoft - Eastsoft.ES32_DFP.1.0.5 + Eastsoft.ES32_DFP.7.2350 http://www.essemi.com IRAM(0x20000000,0x00018000) IROM(0x00000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE @@ -182,6 +184,7 @@ 0 0 0 + 0 0 0 8 @@ -322,6 +325,7 @@ 0 0 1 + 0 0 1 1 -- Gitee