# ignore ModelSim generated files and directories (temp files and so on)
[_@]*

# ignore compilation output of ModelSim
*.mti
*.dat
*.dbs
*.psm
*.bak
*.cmp
*.jpg
#*.html
*.bsf

# ignore simulation output of ModelSim
wlf*
*.wlf
*.vstf
*.ucdb
cov*/
transcript*
vsim.dbg
/Full-Design/MiaoBiao/db
/Full-Design/MiaoBiao/*.qws
/Full-Design/MiaoBiao/*.cdf
/Full-Design/MiaoBiao/*.dpf
/Experiments/adder/*.qsf
/Experiments/adder/*.vwf
*.rpt
*.done
*.smsg
*.summary
*.jdi
*.pin
*.qws
*.sld
*.kpt
*.cdb
*.hdb
*.sof
*.qmsg
*.rdb
*.ddb
*.bpm
*.idb
*.logdb
*.hsd
*.db_info
*.hier_info
*.hif
*.ammdb
*.sci
*.tdb
*.tmw_info
*.json
*.dfp
*.rcfdb
*.dpi
*.hb_info
*.sig
Experiments/adder/incremental_db/README
Experiments/adder/db/adder.smart_action.txt
Experiments/adder/db/adder.lpc.txt
*.tdf
Full-Designs/MiaoBiao/db/MiaoBiao.lpc.txt
Full-Designs/MiaoBiao/db/MiaoBiao.smart_action.txt
Full-Designs/MiaoBiao/incremental_db/README
*.nvd
*.flock
Examples/L3-1/db/adder1bit.cbx.xml
Examples/L3-1/db/adder1bit.lpc.txt
Examples/L3-1/db/adder1bit.smart_action.txt
Examples/L3-1/incremental_db/README
Examples/L3-1/output_files/adder1bit.pof
*.sft
*.vo
*.xrf
*.do
*.ini
Examples/L3-1/simulation/modelsim/msim_transcript
*.xml
Examples/L3-2/db/adder1bit.lpc.txt
Examples/L3-2/db/adder1bit.smart_action.txt
Examples/L3-2/incremental_db/README
Examples/L3-2/output_files/adder1bit.pof
Examples/L3-2/simulation/modelsim/adder1bit_run_msim_rtl_verilog.do.bak1
Examples/L3-2/simulation/modelsim/adder1bit_run_msim_rtl_verilog.do.bak2
Examples/L3-2/simulation/modelsim/msim_transcript
Examples/L3-3/adder.pof
Examples/L3-3/adder_description.txt
Examples/L3-3/db/adder.lpc.txt
Examples/L3-3/db/adder.smart_action.txt
Examples/L3-3/incremental_db/README
Examples/L3-4/db/adder4bits.lpc.txt
Examples/L3-4/db/adder4bits.smart_action.txt
Examples/L3-4/incremental_db/README
Examples/L3-4/output_files/adder4bits.pof
*.qarlog
*.sdo
*.csd
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*.bak5
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Homeworks/L5Homework/method1/db/FullAdder.lpc.txt
Homeworks/L5Homework/method1/db/FullAdder.smart_action.txt
Homeworks/L5Homework/method1/incremental_db/README
Homeworks/L5Homework/method1/simulation/modelsim/msim_transcript
Homeworks/L5Homework/method2/db/FullAdder.lpc.txt
Homeworks/L5Homework/method2/db/FullAdder.smart_action.txt
Homeworks/L5Homework/method2/incremental_db/README
Homeworks/L5Homework/method2/simulation/modelsim/msim_transcript
Homeworks/L6Homework/vote3Prj/db/vote3.lpc.txt
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Homeworks/L6Homework/vote3Prj/incremental_db/README
Homeworks/L7Homework/mult_8BitsPrj1/db/mult_8Bits.lpc.txt
Homeworks/L7Homework/mult_8BitsPrj1/db/mult_8Bits.smart_action.txt
Homeworks/L7Homework/mult_8BitsPrj1/incremental_db/README
Examples/L7-3/schTopPrj/db/acc.lpc.txt
Examples/L7-3/schTopPrj/db/acc.smart_action.txt
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Examples/L7-3/schTopPrj/simulation/modelsim/msim_transcript
Examples/L7-3/txtTopPrj/db/acc.lpc.txt
Examples/L7-3/txtTopPrj/db/acc.smart_action.txt
Examples/L7-3/txtTopPrj/incremental_db/README
Examples/L7-3/txtTopPrj/simulation/modelsim/acc.vt
Examples/L7-3/txtTopPrj/simulation/modelsim/msim_transcript
Examples/L7-5/ttl74138Prj/db/ttl74138.lpc.txt
Examples/L7-5/ttl74138Prj/db/ttl74138.smart_action.txt
Examples/L7-5/ttl74138Prj/incremental_db/README
Examples/L7-5/ttl74138Prj/simulation/modelsim/msim_transcript
Examples/L7-5/ttl74148Prj/db/ttl74148.lpc.txt
Examples/L7-5/ttl74148Prj/db/ttl74148.smart_action.txt
Examples/L7-5/ttl74148Prj/incremental_db/README
Examples/L7-3/txtTopPrj/quartus_nativelink_synthesis.log
Homeworks/L9Homework/multiplier/db/multiplier8Bits.lpc.txt
Homeworks/L9Homework/multiplier/db/multiplier8Bits.smart_action.txt
Homeworks/L9Homework/multiplier/db/multiplier8Bits.smp_dump.txt
Homeworks/L9Homework/multiplier/incremental_db/README
Homeworks/L9Homework/multiplier/simulation/modelsim/msim_transcript
*.bak10
*.bak11
*.bak7
*.bak8
*.bak9
Examples/L9-5/multiplier/multiplier_Fsm_Prj/db/multiplier8Bits.lpc.txt
Examples/L9-5/multiplier/multiplier_Fsm_Prj/db/multiplier8Bits.smart_action.txt
Examples/L9-5/multiplier/multiplier_Fsm_Prj/db/multiplier8Bits.smp_dump.txt
Examples/L9-5/multiplier/multiplier_Fsm_Prj/incremental_db/README
Examples/L9-5/multiplier/multiplier_Fsm_Prj/simulation/modelsim/msim_transcript
Examples/L9-5/multiplier/multiplier_ShiftAdd_Prj/db/multiplier8Bits.lpc.txt
Examples/L9-5/multiplier/multiplier_ShiftAdd_Prj/db/multiplier8Bits.smart_action.txt
Examples/L9-5/multiplier/multiplier_ShiftAdd_Prj/incremental_db/README
Examples/L9-5/multiplier/multiplier_ShiftAdd_Prj/simulation/modelsim/msim_transcript
Examples/L9-6/mod5Cnt_FsmPrj/db/mod5Cnt_Fsm.lpc.txt
Examples/L9-6/mod5Cnt_FsmPrj/db/mod5Cnt_Fsm.smart_action.txt
Examples/L9-6/mod5Cnt_FsmPrj/incremental_db/README
Examples/L9-6/mod5CntPrj/db/mod5Cnt.lpc.txt
Examples/L9-6/mod5CntPrj/db/mod5Cnt.smart_action.txt
Examples/L9-6/mod5CntPrj/incremental_db/README
Examples/L9-6/mod5Cnt_FsmPrj/db/mod5Cnt_Fsm.smp_dump.txt
Experiments/adder/simulation/modelsim/adder.vt
Experiments/adder/simulation/modelsim/msim_transcript
Experiments/DDisplay/db/ddisplay8.lpc.txt
Experiments/DDisplay/db/ddisplay8.smart_action.txt
*.pof
Experiments/DDisplay/incremental_db/README
Full-Designs/MiaoBiao/switch.v
vivado.jou
vivado.log
*.str
.xil
Lab1_flashLED.cache
Lab1_flashLED.hw
Lab1_flashLED.runs
Lab1_flashLED.sim
Lab2_Smart_responder.cache
Lab2_Smart_responder.hw
Lab2_Smart_responder.runs
Lab2_Smart_responder.sim
Lab3_div_clk.cache
Lab3_div_clk.hw
Lab3_div_clk.runs
Lab3_div_clk.sim
Lab4_filter.cache
Lab4_filter.hw
Lab4_filter.runs
Lab4_filter.sim
Lab4_filter.ip_user_files
Lab4_filter.srcs
lab5_uart.cache
lab5_uart.hw
lab5_uart.runs
lab5_uart.sim
lab5_uart.ip_user_files
lab5_uart.srcs
Lab6_display_vga.cache
Lab6_display_vga.hw
Lab6_display_vga.runs
Lab6_display_vga.sim
Lab6_display_vga.ip_user_files
Lab6_display_vga.srcs
Lab7_bt_uart.cache
Lab7_bt_uart.hw
Lab7_bt_uart.runs
Lab7_bt_uart.sim
Lab7_bt_uart.ip_user_files
Lab7_bt_uart.srcs
Lab8_Microblaze_lab.cache
Lab8_Microblaze_lab.hw
Lab8_Microblaze_lab.runs
Lab8_Microblaze_lab.sim
Lab8_Microblaze_lab.ip_user_files
Lab8_Microblaze_lab.srcs
Lab8_Microblaze_lab.ioplanning
Lab8_Microblaze_lab.sdk
expHW
FullAdder_1bit.cache
FullAdder_1bit.hw
FullAdder_1bit.runs
FullAdder_1bit.sim
FullAdder_1bit.ip_user_files
FullAdder_1bit.srcs
FullAdder_1bit.ioplanning
FullAdder_1bit.sdk


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2020-Spring/Examples/L9-6/mod5Cnt_FsmPrj/db/mod5Cnt_Fsm.lpc.html
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CourseExample/L4-6_add4_bin/vivado_prj/add4_bin.sim/sim_1/impl/timing/xsim/xsim.dir/xil_defaultlib/add4_bin.sdb
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Experiments/exp7-perfect/TrafficLights_top/TrafficLights_top.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
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Experiments/exp7/TrafficLights/TrafficLights.sim/sim_1/behav/xsim/xsim.dir/TrafficLights_tb_behav/xsimk.exe
Experiments/exp7/TrafficLights/TrafficLights.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/fsm_traffic.sdb
Experiments/exp7/TrafficLights/TrafficLights.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb
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Experiments/exp7/TrafficLights/TrafficLights.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tafficlights_top.sdb
Experiments/exp7/TrafficLights/TrafficLights.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
Experiments/exp7/TrafficLights/TrafficLights_tb_behav.wcfg
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Experiments/exp8/SRC有问题待检查.zip
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Experiments/StopWatch_VerilogSource/HMS_Clock/HMS_Clock.sim/sim_1/behav/xsim/xsim.dir/StopWatch_top_behav/xsimk.exe
Experiments/StopWatch_VerilogSource/HMS_Clock/HMS_Clock.sim/sim_1/behav/xsim/xsim.dir/StopWatch_top_tb_behav/obj/xsim_0.win64.obj
Experiments/StopWatch_VerilogSource/HMS_Clock/HMS_Clock.sim/sim_1/behav/xsim/xsim.dir/StopWatch_top_tb_behav/obj/xsim_1.c
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Experiments/StopWatch_VerilogSource/HMS_Clock/HMS_Clock.sim/sim_1/behav/xsim/xsim.dir/StopWatch_top_tb_behav/xsim.dbg
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Experiments/StopWatch_VerilogSource/HMS_Clock/HMS_Clock.sim/sim_1/synth/timing/xsim/StopWatch_top_tb_time_synth.wdb
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EGO1_Lab/Lab9_Soundout/SoundOut/MatLab/hdlsrc/filter.v
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EGO1_Lab/Lab9_Soundout/SoundOut/SoundOut.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/filter.sdb
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EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/dds_Cosine_synth_1/.vivado.end.rst
EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/dds_Cosine_synth_1/.Vivado_Synthesis.queue.rst
EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/dds_Cosine_synth_1/dds_Cosine.dcp
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EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/.opt_design.begin.rst
EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/.opt_design.end.rst
EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/.place_design.begin.rst
EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/.place_design.end.rst
EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/.route_design.begin.rst
EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/.route_design.end.rst
EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/.vivado.begin.rst
EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/.vivado.end.rst
EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/.Vivado_Implementation.queue.rst
EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/.write_bitstream.begin.rst
EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/.write_bitstream.end.rst
EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/htr.txt
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EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/ISEWrap.js
EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/ISEWrap.sh
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EGO1_Lab/Lab9_Soundout/SoundOut_Tcl/work_Prj/SoundOut/SoundOut.runs/impl_1/SoundOut_methodology_drc_routed.pb
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EGO1_Lab/VGA_BAR/Vivado_Prj/VGA_BAR.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
EGO1_Lab/VGA_BAR/Vivado_Prj/VGA_BAR.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
EGO1_Lab/VGA_BAR/Vivado_Prj/VGA_BAR.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
EGO1_Lab/VGA_BAR/Vivado_Prj/VGA_BAR.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
EGO1_Lab/VGA_BAR/Vivado_Prj/VGA_BAR.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt
EGO1_Lab/VGA_BAR/Vivado_Prj/VGA_BAR.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh
EGO1_Lab/VGA_BAR/Vivado_Prj/VGA_BAR.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh
EGO1_Lab/VGA_BAR/Vivado_Prj/VGA_BAR.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh
EGO1_Lab/VGA_BAR/Vivado_Prj/VGA_BAR.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh
EGO1_Lab/VGA_BAR/Vivado_Prj/VGA_BAR.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh
EGO1_Lab/VGA_BAR/Vivado_Prj/VGA_BAR.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh
Ex15/adder/adder.cache/wt/gui_handlers.wdf
Ex15/adder/adder.cache/wt/java_command_handlers.wdf
Ex15/adder/adder.cache/wt/project.wpc
Ex15/adder/adder.cache/wt/synthesis.wdf
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Ex15/BCD_CNT/BCDCnt100.cache/wt/gui_handlers.wdf
Ex15/BCD_CNT/BCDCnt100.cache/wt/java_command_handlers.wdf
Ex15/BCD_CNT/BCDCnt100.cache/wt/project.wpc
Ex15/BCD_CNT/BCDCnt100.cache/wt/synthesis.wdf
Ex15/BCD_CNT/BCDCnt100.cache/wt/xsim.wdf
Ex15/BCD_CNT/BCDCnt100.hw/BCDCnt100.lpr
Ex15/BCD_CNT/BCDCnt100.ip_user_files/README.txt
Ex15/BCD_CNT/BCDCnt100.sim/sim_1/behav/xsim/BCDCnt100_tb.tcl
Ex15/BCD_CNT/BCDCnt100.sim/sim_1/behav/xsim/BCDCnt100_tb_behav.wdb
Ex15/BCD_CNT/BCDCnt100.sim/sim_1/behav/xsim/BCDCnt100_tb_vlog.prj
Ex15/BCD_CNT/BCDCnt100.sim/sim_1/behav/xsim/compile.bat
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Ex15/ttl74148/ttl74148.cache/wt/gui_handlers.wdf
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