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From 740a1e791175987e28cc39dbd11e3fc152ffc40b Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Fri, 14 Jan 2022 10:54:55 +0100
Subject: [PATCH] x86: reduce AVX512 FP set of insns decoded through
vex_w_table[]
Like for AVX512-FP16, there's not that many FP insns where going through
this table is easier / cheaper than using suitable macros. Utilize %XS
and %XD more to eliminate a fair number of table entries.
While doing this I noticed a few anomalies. Where lines get touched /
moved anyway, these are being addressed right here:
- vmovshdup used EXx for its 2nd operand, thus displaying seemingly
valid broadcast when EVEX.b is set with a memory operand; use
EXEvexXNoBcst instead just like vmovsldup already does
- vmovlhps used EXx for its 3rd operand, when all sibling entries use
EXq; switch to EXq there for consistency (the two differ only for
memory operands)
diff --git a/opcodes/i386-dis-evex-mod.h b/opcodes/i386-dis-evex-mod.h
index 7a372ce8c0b..2d35bf2a589 100644
--- a/opcodes/i386-dis-evex-mod.h
+++ b/opcodes/i386-dis-evex-mod.h
@@ -1,7 +1,7 @@
{
/* MOD_EVEX_0F12_PREFIX_0 */
{ "vmovlpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F12_P_0_M_1) },
+ { "vmovhlp%XS", { XMM, Vex, EXq }, 0 },
},
{
/* MOD_EVEX_0F12_PREFIX_2 */
@@ -14,7 +14,7 @@
{
/* MOD_EVEX_0F16_PREFIX_0 */
{ "vmovhpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F16_P_0_M_1) },
+ { "vmovlhp%XS", { XMM, Vex, EXq }, 0 },
},
{
/* MOD_EVEX_0F16_PREFIX_2 */
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index 64a43ce02a1..fc5439a1fec 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -1,28 +1,28 @@
/* PREFIX_EVEX_0F10 */
{
{ "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F10_P_1) },
+ { "vmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
{ "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F10_P_3) },
+ { "vmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
},
/* PREFIX_EVEX_0F11 */
{
{ "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F11_P_1) },
+ { "vmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
{ "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F11_P_3) },
+ { "vmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
},
/* PREFIX_EVEX_0F12 */
{
{ MOD_TABLE (MOD_EVEX_0F12_PREFIX_0) },
- { VEX_W_TABLE (EVEX_W_0F12_P_1) },
+ { "vmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
{ MOD_TABLE (MOD_EVEX_0F12_PREFIX_2) },
- { VEX_W_TABLE (EVEX_W_0F12_P_3) },
+ { "vmov%XDdup", { XM, EXymmq }, 0 },
},
/* PREFIX_EVEX_0F16 */
{
{ MOD_TABLE (MOD_EVEX_0F16_PREFIX_0) },
- { VEX_W_TABLE (EVEX_W_0F16_P_1) },
+ { "vmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
{ MOD_TABLE (MOD_EVEX_0F16_PREFIX_2) },
},
/* PREFIX_EVEX_0F2A */
@@ -35,64 +35,64 @@
/* PREFIX_EVEX_0F51 */
{
{ "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F51_P_1) },
+ { "vsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F51_P_3) },
+ { "vsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F58 */
{
{ "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F58_P_1) },
+ { "vadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F58_P_3) },
+ { "vadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F59 */
{
{ "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F59_P_1) },
+ { "vmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F59_P_3) },
+ { "vmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5A */
{
- { VEX_W_TABLE (EVEX_W_0F5A_P_0) },
- { VEX_W_TABLE (EVEX_W_0F5A_P_1) },
- { VEX_W_TABLE (EVEX_W_0F5A_P_2) },
- { VEX_W_TABLE (EVEX_W_0F5A_P_3) },
+ { "vcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
+ { "vcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+ { "vcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
+ { "vcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5B */
{
{ VEX_W_TABLE (EVEX_W_0F5B_P_0) },
- { VEX_W_TABLE (EVEX_W_0F5B_P_1) },
- { VEX_W_TABLE (EVEX_W_0F5B_P_2) },
+ { "vcvttp%XS2dq", { XM, EXx, EXxEVexS }, 0 },
+ { "vcvtp%XS2dq", { XM, EXx, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5C */
{
{ "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5C_P_1) },
+ { "vsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5C_P_3) },
+ { "vsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5D */
{
{ "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5D_P_1) },
+ { "vmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
{ "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5D_P_3) },
+ { "vmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_0F5E */
{
{ "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5E_P_1) },
+ { "vdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5E_P_3) },
+ { "vdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5F */
{
{ "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5F_P_1) },
+ { "vmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
{ "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5F_P_3) },
+ { "vmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_0F6F */
{
@@ -152,16 +152,16 @@
/* PREFIX_EVEX_0FC2 */
{
{ "vcmppX", { MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0FC2_P_1) },
+ { "vcmps%XS", { MaskG, VexScalar, EXd, EXxEVexS, CMP }, 0 },
{ "vcmppX", { MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0FC2_P_3) },
+ { "vcmps%XD", { MaskG, VexScalar, EXq, EXxEVexS, CMP }, 0 },
},
/* PREFIX_EVEX_0FE6 */
{
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0FE6_P_1) },
- { VEX_W_TABLE (EVEX_W_0FE6_P_2) },
- { VEX_W_TABLE (EVEX_W_0FE6_P_3) },
+ { "vcvttp%XD2dq%XY", { XMxmmq, EXx, EXxEVexS }, 0 },
+ { "vcvtp%XD2dq%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F3810 */
{
@@ -185,7 +185,7 @@
{
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F3813_P_1) },
- { VEX_W_TABLE (EVEX_W_0F3813_P_2) },
+ { "vcvtph2p%XS", { XM, EXxmmq, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_0F3814 */
{
@@ -322,7 +322,7 @@
/* PREFIX_EVEX_0F3852 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_0F3852_P_1) },
+ { "vdpbf16p%XS", { XM, Vex, EXx }, 0 },
{ "vpdpwssd", { XM, Vex, EXx }, 0 },
{ "vp4dpwssd", { XM, Vex, EXxmm }, 0 },
},
@@ -343,9 +343,9 @@
/* PREFIX_EVEX_0F3872 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_0F3872_P_1) },
+ { "vcvtnep%XS2bf16%XY", { XMxmmq, EXx }, 0 },
{ VEX_W_TABLE (EVEX_W_0F3872_P_2) },
- { VEX_W_TABLE (EVEX_W_0F3872_P_3) },
+ { "vcvtne2p%XS2bf16", { XM, Vex, EXx}, 0 },
},
/* PREFIX_EVEX_0F389A */
{
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
index fc0a0791d1d..9b4bb6a2924 100644
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -1,136 +1,8 @@
- /* EVEX_W_0F10_P_1 */
- {
- { "vmovss", { XMScalar, VexScalarR, EXd }, 0 },
- },
- /* EVEX_W_0F10_P_3 */
- {
- { Bad_Opcode },
- { "vmovsd", { XMScalar, VexScalarR, EXq }, 0 },
- },
- /* EVEX_W_0F11_P_1 */
- {
- { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
- },
- /* EVEX_W_0F11_P_3 */
- {
- { Bad_Opcode },
- { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
- },
- /* EVEX_W_0F12_P_0_M_1 */
- {
- { "vmovhlps", { XMM, Vex, EXq }, 0 },
- },
- /* EVEX_W_0F12_P_1 */
- {
- { "vmovsldup", { XM, EXEvexXNoBcst }, 0 },
- },
- /* EVEX_W_0F12_P_3 */
- {
- { Bad_Opcode },
- { "vmovddup", { XM, EXymmq }, 0 },
- },
- /* EVEX_W_0F16_P_0_M_1 */
- {
- { "vmovlhps", { XMM, Vex, EXx }, 0 },
- },
- /* EVEX_W_0F16_P_1 */
- {
- { "vmovshdup", { XM, EXx }, 0 },
- },
- /* EVEX_W_0F51_P_1 */
- {
- { "vsqrtss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F51_P_3 */
- {
- { Bad_Opcode },
- { "vsqrtsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F58_P_1 */
- {
- { "vaddss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F58_P_3 */
- {
- { Bad_Opcode },
- { "vaddsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F59_P_1 */
- {
- { "vmulss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F59_P_3 */
- {
- { Bad_Opcode },
- { "vmulsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5A_P_0 */
- {
- { "vcvtps2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5A_P_1 */
- {
- { "vcvtss2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5A_P_2 */
- {
- { Bad_Opcode },
- { "vcvtpd2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5A_P_3 */
- {
- { Bad_Opcode },
- { "vcvtsd2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
/* EVEX_W_0F5B_P_0 */
{
{ "vcvtdq2ps", { XM, EXx, EXxEVexR }, 0 },
{ "vcvtqq2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
},
- /* EVEX_W_0F5B_P_1 */
- {
- { "vcvttps2dq", { XM, EXx, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5B_P_2 */
- {
- { "vcvtps2dq", { XM, EXx, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5C_P_1 */
- {
- { "vsubss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5C_P_3 */
- {
- { Bad_Opcode },
- { "vsubsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5D_P_1 */
- {
- { "vminss", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5D_P_3 */
- {
- { Bad_Opcode },
- { "vminsd", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5E_P_1 */
- {
- { "vdivss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5E_P_3 */
- {
- { Bad_Opcode },
- { "vdivsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5F_P_1 */
- {
- { "vmaxss", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5F_P_3 */
- {
- { Bad_Opcode },
- { "vmaxsd", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
- },
/* EVEX_W_0F62 */
{
{ "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
@@ -258,15 +130,6 @@
{ "vmovdqu8", { EXxS, XM }, 0 },
{ "vmovdqu16", { EXxS, XM }, 0 },
},
- /* EVEX_W_0FC2_P_1 */
- {
- { "vcmpss", { MaskG, VexScalar, EXd, EXxEVexS, CMP }, 0 },
- },
- /* EVEX_W_0FC2_P_3 */
- {
- { Bad_Opcode },
- { "vcmpsd", { MaskG, VexScalar, EXq, EXxEVexS, CMP }, 0 },
- },
/* EVEX_W_0FD2 */
{
{ "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
@@ -291,16 +154,6 @@
{ "vcvtdq2pd", { XM, EXEvexHalfBcstXmmq }, 0 },
{ "vcvtqq2pd", { XM, EXx, EXxEVexR }, 0 },
},
- /* EVEX_W_0FE6_P_2 */
- {
- { Bad_Opcode },
- { "vcvttpd2dq%XY", { XMxmmq, EXx, EXxEVexS }, 0 },
- },
- /* EVEX_W_0FE6_P_3 */
- {
- { Bad_Opcode },
- { "vcvtpd2dq%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
- },
/* EVEX_W_0FE7 */
{
{ "vmovntdq", { EXEvexXNoBcst, XM }, PREFIX_DATA },
@@ -332,11 +185,6 @@
{
{ "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
},
- /* EVEX_W_0F380D */
- {
- { Bad_Opcode },
- { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
- },
/* EVEX_W_0F3810_P_1 */
{
{ "vpmovuswb", { EXxmmq, XM }, 0 },
@@ -368,10 +216,6 @@
{
{ "vpmovusdw", { EXxmmq, XM }, 0 },
},
- /* EVEX_W_0F3813_P_2 */
- {
- { "vcvtph2ps", { XM, EXxmmq, EXxEVexS }, 0 },
- },
/* EVEX_W_0F3814_P_1 */
{
{ "vpmovusqw", { EXxmmqd, XM }, 0 },
@@ -492,11 +336,6 @@
{
{ MOD_TABLE (MOD_EVEX_0F383A_P_1_W_0) },
},
- /* EVEX_W_0F3852_P_1 */
- {
- { "vdpbf16ps", { XM, Vex, EXx }, 0 },
- { Bad_Opcode },
- },
/* EVEX_W_0F3859 */
{
{ "vbroadcasti32x2", { XM, EXq }, PREFIX_DATA },
@@ -517,21 +356,11 @@
{ Bad_Opcode },
{ "vpshldvw", { XM, Vex, EXx }, PREFIX_DATA },
},
- /* EVEX_W_0F3872_P_1 */
- {
- { "vcvtneps2bf16%XY", { XMxmmq, EXx }, 0 },
- { Bad_Opcode },
- },
/* EVEX_W_0F3872_P_2 */
{
{ Bad_Opcode },
{ "vpshrdvw", { XM, Vex, EXx }, 0 },
},
- /* EVEX_W_0F3872_P_3 */
- {
- { "vcvtne2ps2bf16", { XM, Vex, EXx}, 0 },
- { Bad_Opcode },
- },
/* EVEX_W_0F387A */
{
{ MOD_TABLE (MOD_EVEX_0F387A_W_0) },
@@ -545,21 +374,6 @@
{ Bad_Opcode },
{ "vpmultishiftqb", { XM, Vex, EXx }, PREFIX_DATA },
},
- /* EVEX_W_0F3A05 */
- {
- { Bad_Opcode },
- { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
- },
- /* EVEX_W_0F3A09 */
- {
- { Bad_Opcode },
- { "vrndscalepd", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA },
- },
- /* EVEX_W_0F3A0B */
- {
- { Bad_Opcode },
- { "vrndscalesd", { XMScalar, VexScalar, EXq, EXxEVexS, Ib }, PREFIX_DATA },
- },
/* EVEX_W_0F3A18_L_n */
{
{ "vinsertf32x4", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 11cc257bb2e..5d621cf1557 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -307,7 +307,7 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
{ VEX_W_TABLE (VEX_W_0F380C) },
- { VEX_W_TABLE (EVEX_W_0F380D) },
+ { "vpermilp%XD", { XM, Vex, EXx }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
@@ -589,14 +589,14 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ "valign%DQ", { XM, Vex, EXx, Ib }, PREFIX_DATA },
{ VEX_W_TABLE (VEX_W_0F3A04) },
- { VEX_W_TABLE (EVEX_W_0F3A05) },
+ { "vpermilp%XD", { XM, EXx, Ib }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
/* 08 */
{ PREFIX_TABLE (PREFIX_EVEX_0F3A08) },
- { VEX_W_TABLE (EVEX_W_0F3A09) },
+ { "vrndscalep%XD", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA },
{ PREFIX_TABLE (PREFIX_EVEX_0F3A0A) },
- { VEX_W_TABLE (EVEX_W_0F3A0B) },
+ { "vrndscales%XD", { XMScalar, VexScalar, EXq, EXxEVexS, Ib }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index afc3743e4e8..ad560b1899c 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1621,36 +1621,7 @@ enum
VEX_W_0FXOP_09_E2_L_0,
VEX_W_0FXOP_09_E3_L_0,
- EVEX_W_0F10_P_1,
- EVEX_W_0F10_P_3,
- EVEX_W_0F11_P_1,
- EVEX_W_0F11_P_3,
- EVEX_W_0F12_P_0_M_1,
- EVEX_W_0F12_P_1,
- EVEX_W_0F12_P_3,
- EVEX_W_0F16_P_0_M_1,
- EVEX_W_0F16_P_1,
- EVEX_W_0F51_P_1,
- EVEX_W_0F51_P_3,
- EVEX_W_0F58_P_1,
- EVEX_W_0F58_P_3,
- EVEX_W_0F59_P_1,
- EVEX_W_0F59_P_3,
- EVEX_W_0F5A_P_0,
- EVEX_W_0F5A_P_1,
- EVEX_W_0F5A_P_2,
- EVEX_W_0F5A_P_3,
EVEX_W_0F5B_P_0,
- EVEX_W_0F5B_P_1,
- EVEX_W_0F5B_P_2,
- EVEX_W_0F5C_P_1,
- EVEX_W_0F5C_P_3,
- EVEX_W_0F5D_P_1,
- EVEX_W_0F5D_P_3,
- EVEX_W_0F5E_P_1,
- EVEX_W_0F5E_P_3,
- EVEX_W_0F5F_P_1,
- EVEX_W_0F5F_P_3,
EVEX_W_0F62,
EVEX_W_0F66,
EVEX_W_0F6A,
@@ -1678,15 +1649,11 @@ enum
EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2,
EVEX_W_0F7F_P_3,
- EVEX_W_0FC2_P_1,
- EVEX_W_0FC2_P_3,
EVEX_W_0FD2,
EVEX_W_0FD3,
EVEX_W_0FD4,
EVEX_W_0FD6,
EVEX_W_0FE6_P_1,
- EVEX_W_0FE6_P_2,
- EVEX_W_0FE6_P_3,
EVEX_W_0FE7,
EVEX_W_0FF2,
EVEX_W_0FF3,
@@ -1694,7 +1661,7 @@ enum
EVEX_W_0FFA,
EVEX_W_0FFB,
EVEX_W_0FFE,
- EVEX_W_0F380D,
+
EVEX_W_0F3810_P_1,
EVEX_W_0F3810_P_2,
EVEX_W_0F3811_P_1,
@@ -1702,7 +1669,6 @@ enum
EVEX_W_0F3812_P_1,
EVEX_W_0F3812_P_2,
EVEX_W_0F3813_P_1,
- EVEX_W_0F3813_P_2,
EVEX_W_0F3814_P_1,
EVEX_W_0F3815_P_1,
EVEX_W_0F3819_L_n,
@@ -1731,21 +1697,15 @@ enum
EVEX_W_0F3835_P_2,
EVEX_W_0F3837,
EVEX_W_0F383A_P_1,
- EVEX_W_0F3852_P_1,
EVEX_W_0F3859,
EVEX_W_0F385A_M_0_L_n,
EVEX_W_0F385B_M_0_L_2,
EVEX_W_0F3870,
- EVEX_W_0F3872_P_1,
EVEX_W_0F3872_P_2,
- EVEX_W_0F3872_P_3,
EVEX_W_0F387A,
EVEX_W_0F387B,
EVEX_W_0F3883,
- EVEX_W_0F3A05,
- EVEX_W_0F3A09,
- EVEX_W_0F3A0B,
EVEX_W_0F3A18_L_n,
EVEX_W_0F3A19_L_n,
EVEX_W_0F3A1A_L_2,
--
2.33.0
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