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OpenGADL-Model

Python

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OpenGADL-Data

Python

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OpenGADL-Model-Pro

Python

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• 0
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My_pictures

Python

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ysyxsoc

projects/soc目录下存放了接入ysyxSoC的示例程序。源码中只有一个占位符，能够通过编译但不能正常运行。 要使用该框架，需要先按照 ysyx SoC 的 readme 完成 命名规范 和 CPU 内部修改 两个步骤，得到 ysyx_21xxxx.v，

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chungus-2-assembler

Assembler and example programs for the CHUNGUS 2 Minecraft CPU. 这是一个红石CPU的汇编语言工具。CHUNGUS即Computational Humongous Unconventional Number and Graphic...

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StochasticNet

Scala

红石数电，官方，RCNN 老巢！

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RISC-V-CPU

Zhou Fan (范舟) This project is a RISC-V CPU with 5-stage pipeline implemented in Verilog HDL, which is a course project of Computer Architecture, A...

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rocket-chip

Scala

This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core. For more information on Rocket Chip, please con...

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buildroot

We also now have support for block devices, so you can also boot from an ext2 image created by buildroot.

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verilator

Verilog

Verilator 是一个高性能 Verilog HDL 模拟器与 lint 系统，用户编写一个小的 C++/SystemC 封装文件，该文件实例化用户顶层模块的“已验证”模型

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riscv-sodor

Verilog

This repo has been put together to demonstrate a number of simple RISC-V integer pipelines written in Chisel: 1-stage (essentially an ISA simulato...

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core-os-raspi

Rust

A simple operating system in Rust. Not in active development. Refer to https://github.com/skyzh/core-os-riscv This project is based on "rust-raspi...

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EVE_IDE

配套研制了一个集成开发环境-Eve-IDE。这种 IDE 集成了整套 RISC-V GCC 工具链和诸如串口助手之类的常用调试工具，IDE 安装包大小仅 48Mbyte。