<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW1NSR-4C" pn="GW1NSR-LV4CQN48PC6/I5">gw1nsr4c-000</Device>
    <FileList>
        <File path="RTL/fpga_top.v" type="file.verilog" enable="1"/>
        <File path="RTL/gowin_pllvr/gowin_pllvr.v" type="file.verilog" enable="1"/>
        <File path="RTL/pixel_generate.v" type="file.verilog" enable="1"/>
        <File path="../RTL/hdmi_tx_top.v" type="file.verilog" enable="1"/>
        <File path="../RTL/hdmi_tmds_encode.v" type="file.verilog" enable="1"/>
        <File path="../RTL/hdmi_async_fifo.v" type="file.verilog" enable="1"/>
        <File path="../RTL/hdmi_tddr.v" type="file.verilog" enable="1"/>
        <File path="top.cst" type="file.cst" enable="1"/>
        <File path="top.sdc" type="file.sdc" enable="1"/>
    </FileList>
</Project>