• 1
• 0
• 1

ysyx-yzu-hlf

Scala

forked from MuxXing / ysyx-yzu-hlf

Scala

一生一芯计划（2021.9.24开始）

• 1
• 0
• 1

ysyx_210760

Scala

forked from MuxXing / ysyx_210760

Scala

一生一芯3rd提交版本

• 1
• 2
• 0

ysyxsoc

projects/soc目录下存放了接入ysyxSoC的示例程序。源码中只有一个占位符，能够通过编译但不能正常运行。 要使用该框架，需要先按照 ysyx SoC 的 readme 完成 命名规范 和 CPU 内部修改 两个步骤，得到 ysyx_21xxxx.v，

• 1
• 1
• 0

StochasticNet

Scala

红石数电，官方，RCNN 老巢！

• 1
• 0
• 0

RISCV-Accelerator

Verilog

本项目基于RISC-V指令集架构，借助RISC-V Rocket Chip平台设计SoC,并通过协处理器(Rocket Custom Coprocessor，RoCC) 接口，采用高级语言Chisel定制Cordic算法片上加速器，实现自定义指令以完成正余弦函数值计算。注：依赖的rocketc...

• 1
• 0
• 76

XiangShan

Scala

forked from XiangShan / XiangShan

Scala

Open-source high-performance RISC-V processor

• 1
• 1
• 0

rocket-chip

Scala

This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core. For more information on Rocket Chip, please con...

• 1
• 0
• 0

fpga-zynq

Support for Rocket Chip on Zynq FPGAs

• 1
• 0
• 0

testchipip

• 1
• 4
• 2

NutShell

Scala

RISC-V SoC designed by students in UCAS. - Open Source Chip Project by University (OSCPU) Let students design their own chips!

• 1
• 0
• 0

riscv-sodor

Verilog

This repo has been put together to demonstrate a number of simple RISC-V integer pipelines written in Chisel: 1-stage (essentially an ISA simulato...

• 1
• 0
• 0

rc-fpga-zcu

Verilog

fesvr-zynq searching result for google.